DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation
In this paper, we propose a correlation-based background linearity calibration technique to digitally correct the bit weights in successive approximation register (SAR)-assisted analog-to-digital converters (ADCs). Unlike typical dithering-based calibration techniques in which signal dynamic range (...
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2024-01-01
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| Series: | IEEE Open Journal of Circuits and Systems |
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| Online Access: | https://ieeexplore.ieee.org/document/10736969/ |
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| author | Lizhen Zhang Bo Gao Kun-Woo Park Kent Edrian Lozada Raymond Mabilangan Hyeongjin Kim Jianhui Wu Seung-Tak Ryu |
| author_facet | Lizhen Zhang Bo Gao Kun-Woo Park Kent Edrian Lozada Raymond Mabilangan Hyeongjin Kim Jianhui Wu Seung-Tak Ryu |
| author_sort | Lizhen Zhang |
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| description | In this paper, we propose a correlation-based background linearity calibration technique to digitally correct the bit weights in successive approximation register (SAR)-assisted analog-to-digital converters (ADCs). Unlike typical dithering-based calibration techniques in which signal dynamic range (DR) is unavoidably reduced, in this work, a small dither signal is injected into the input path by a simple switching scheme. The associated DR loss is avoided by the back-end redundancy. We also describe a capacitor-scanning dither method to accomplish simultaneous and independent identification of multiple bit weights. In addition, a digital-domain input-interference cancellation (IIC) technique is proposed to accelerate the convergence speed of the correlation-based calibration. The proposed calibration and acceleration techniques are analyzed by using both theoretical formulation and system simulation. The simulation results are presented with a 12-bit SAR-assisted two-stage pipeline ADC model. Owing to our proposed calibration, the spurious-free dynamic range (SFDR) increased from 60.1 to 84.8 dB and the signal to noise and distortion ratio (SNDR) improved from 55.4 to 72.5 dB. By comparing the cases with and without the proposed IIC technique, a <inline-formula> <tex-math notation="LaTeX">$50\times $ </tex-math></inline-formula> reduction in convergence cycle could be achieved. The proposed calibration technique can be utilized to overcome the inherent DAC mismatch and residue gain errors to implement high-linearity ADCs, such as SAR-assisted ADCs in many different applications. |
| format | Article |
| id | doaj-art-85e74ffc8e6f4519873f5954b8bf762e |
| institution | Kabale University |
| issn | 2644-1225 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
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| series | IEEE Open Journal of Circuits and Systems |
| spelling | doaj-art-85e74ffc8e6f4519873f5954b8bf762e2025-01-21T00:02:57ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252024-01-01534936410.1109/OJCAS.2024.348680910736969DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference CancellationLizhen Zhang0https://orcid.org/0000-0001-5365-2465Bo Gao1https://orcid.org/0000-0002-2931-1270Kun-Woo Park2https://orcid.org/0009-0002-7059-074XKent Edrian Lozada3https://orcid.org/0000-0002-5858-0453Raymond Mabilangan4https://orcid.org/0009-0009-3510-7741Hyeongjin Kim5https://orcid.org/0009-0002-7319-585XJianhui Wu6https://orcid.org/0000-0002-7878-498XSeung-Tak Ryu7https://orcid.org/0000-0002-6947-7785School of Electronic Science and Engineering, Southeast University, Nanjing, ChinaSchool of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South KoreaSchool of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South KoreaSchool of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South KoreaSchool of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South KoreaSchool of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South KoreaSchool of Electronic Science and Engineering, Southeast University, Nanjing, ChinaSchool of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South KoreaIn this paper, we propose a correlation-based background linearity calibration technique to digitally correct the bit weights in successive approximation register (SAR)-assisted analog-to-digital converters (ADCs). Unlike typical dithering-based calibration techniques in which signal dynamic range (DR) is unavoidably reduced, in this work, a small dither signal is injected into the input path by a simple switching scheme. The associated DR loss is avoided by the back-end redundancy. We also describe a capacitor-scanning dither method to accomplish simultaneous and independent identification of multiple bit weights. In addition, a digital-domain input-interference cancellation (IIC) technique is proposed to accelerate the convergence speed of the correlation-based calibration. The proposed calibration and acceleration techniques are analyzed by using both theoretical formulation and system simulation. The simulation results are presented with a 12-bit SAR-assisted two-stage pipeline ADC model. Owing to our proposed calibration, the spurious-free dynamic range (SFDR) increased from 60.1 to 84.8 dB and the signal to noise and distortion ratio (SNDR) improved from 55.4 to 72.5 dB. By comparing the cases with and without the proposed IIC technique, a <inline-formula> <tex-math notation="LaTeX">$50\times $ </tex-math></inline-formula> reduction in convergence cycle could be achieved. The proposed calibration technique can be utilized to overcome the inherent DAC mismatch and residue gain errors to implement high-linearity ADCs, such as SAR-assisted ADCs in many different applications.https://ieeexplore.ieee.org/document/10736969/Digital background calibrationbit weightdynamic rangeSAR-assisted ADCdither injectioninput-interference cancellation |
| spellingShingle | Lizhen Zhang Bo Gao Kun-Woo Park Kent Edrian Lozada Raymond Mabilangan Hyeongjin Kim Jianhui Wu Seung-Tak Ryu DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation IEEE Open Journal of Circuits and Systems Digital background calibration bit weight dynamic range SAR-assisted ADC dither injection input-interference cancellation |
| title | DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation |
| title_full | DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation |
| title_fullStr | DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation |
| title_full_unstemmed | DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation |
| title_short | DR Loss-Free Dithering-Based Digital Background Linearity Calibration for SAR-Assisted Multi-Stage ADCs With Digital Input-Interference Cancellation |
| title_sort | dr loss free dithering based digital background linearity calibration for sar assisted multi stage adcs with digital input interference cancellation |
| topic | Digital background calibration bit weight dynamic range SAR-assisted ADC dither injection input-interference cancellation |
| url | https://ieeexplore.ieee.org/document/10736969/ |
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