Stego on FPGA: An IWT Approach

A reconfigurable hardware architecture for the implementation of integer wavelet transform (IWT) based adaptive random image steganography algorithm is proposed. The Haar-IWT was used to separate the subbands namely, LL, LH, HL, and HH, from 8×8 pixel blocks and the encrypted secret data is hidden i...

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Main Authors: Balakrishnan Ramalingam, Rengarajan Amirtharajan, John Bosco Balaguru Rayappan
Format: Article
Language:English
Published: Wiley 2014-01-01
Series:The Scientific World Journal
Online Access:http://dx.doi.org/10.1155/2014/192512
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author Balakrishnan Ramalingam
Rengarajan Amirtharajan
John Bosco Balaguru Rayappan
author_facet Balakrishnan Ramalingam
Rengarajan Amirtharajan
John Bosco Balaguru Rayappan
author_sort Balakrishnan Ramalingam
collection DOAJ
description A reconfigurable hardware architecture for the implementation of integer wavelet transform (IWT) based adaptive random image steganography algorithm is proposed. The Haar-IWT was used to separate the subbands namely, LL, LH, HL, and HH, from 8×8 pixel blocks and the encrypted secret data is hidden in the LH, HL, and HH blocks using Moore and Hilbert space filling curve (SFC) scan patterns. Either Moore or Hilbert SFC was chosen for hiding the encrypted data in LH, HL, and HH coefficients, whichever produces the lowest mean square error (MSE) and the highest peak signal-to-noise ratio (PSNR). The fixated random walk’s verdict of all blocks is registered which is nothing but the furtive key. Our system took 1.6 µs for embedding the data in coefficient blocks and consumed 34% of the logic elements, 22% of the dedicated logic register, and 2% of the embedded multiplier on Cyclone II field programmable gate array (FPGA).
format Article
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institution Kabale University
issn 2356-6140
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language English
publishDate 2014-01-01
publisher Wiley
record_format Article
series The Scientific World Journal
spelling doaj-art-85b5240ce48f4704a3aecf05f3f49e642025-02-03T05:43:40ZengWileyThe Scientific World Journal2356-61401537-744X2014-01-01201410.1155/2014/192512192512Stego on FPGA: An IWT ApproachBalakrishnan Ramalingam0Rengarajan Amirtharajan1John Bosco Balaguru Rayappan2School of Electrical & Electronics Engineering, SASTRA University, Thanjavur 613401, IndiaSchool of Electrical & Electronics Engineering, SASTRA University, Thanjavur 613401, IndiaSchool of Electrical & Electronics Engineering, SASTRA University, Thanjavur 613401, IndiaA reconfigurable hardware architecture for the implementation of integer wavelet transform (IWT) based adaptive random image steganography algorithm is proposed. The Haar-IWT was used to separate the subbands namely, LL, LH, HL, and HH, from 8×8 pixel blocks and the encrypted secret data is hidden in the LH, HL, and HH blocks using Moore and Hilbert space filling curve (SFC) scan patterns. Either Moore or Hilbert SFC was chosen for hiding the encrypted data in LH, HL, and HH coefficients, whichever produces the lowest mean square error (MSE) and the highest peak signal-to-noise ratio (PSNR). The fixated random walk’s verdict of all blocks is registered which is nothing but the furtive key. Our system took 1.6 µs for embedding the data in coefficient blocks and consumed 34% of the logic elements, 22% of the dedicated logic register, and 2% of the embedded multiplier on Cyclone II field programmable gate array (FPGA).http://dx.doi.org/10.1155/2014/192512
spellingShingle Balakrishnan Ramalingam
Rengarajan Amirtharajan
John Bosco Balaguru Rayappan
Stego on FPGA: An IWT Approach
The Scientific World Journal
title Stego on FPGA: An IWT Approach
title_full Stego on FPGA: An IWT Approach
title_fullStr Stego on FPGA: An IWT Approach
title_full_unstemmed Stego on FPGA: An IWT Approach
title_short Stego on FPGA: An IWT Approach
title_sort stego on fpga an iwt approach
url http://dx.doi.org/10.1155/2014/192512
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