Networks on Chips: Structure and Design Methodologies
The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the...
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| Format: | Article |
| Language: | English |
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Wiley
2012-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2012/509465 |
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| _version_ | 1832556279160111104 |
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| author | Wen-Chung Tsai Ying-Cherng Lan Yu-Hen Hu Sao-Jie Chen |
| author_facet | Wen-Chung Tsai Ying-Cherng Lan Yu-Hen Hu Sao-Jie Chen |
| author_sort | Wen-Chung Tsai |
| collection | DOAJ |
| description | The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for on-chip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs. |
| format | Article |
| id | doaj-art-84a988053e3f47c085cbdbfc4bf8e7f4 |
| institution | Kabale University |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2012-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-84a988053e3f47c085cbdbfc4bf8e7f42025-02-03T05:45:48ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552012-01-01201210.1155/2012/509465509465Networks on Chips: Structure and Design MethodologiesWen-Chung Tsai0Ying-Cherng Lan1Yu-Hen Hu2Sao-Jie Chen3Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, TaiwanGraduate Institute of Electronics Engineering, National Taiwan University, Taipei 106, TaiwanDepartment of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, WI 53706-1691, USADepartment of Electrical Engineering and Graduate Institute of Electronics Enginering, National Taiwan University, Taipei 106, TaiwanThe next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. Such a many-core system requires high-performance interconnections to transfer data among the cores on the chip. Traditional system components interface with the interconnection backbone via a bus interface. This interconnection backbone can be an on-chip bus or multilayer bus architecture. With the advent of many-core architectures, the bus architecture becomes the performance bottleneck of the on-chip interconnection framework. In contrast, network on chip (NoC) becomes a promising on-chip communication infrastructure, which is commonly considered as an aggressive long-term approach for on-chip communications. Accordingly, this paper first discusses several common architectures and prevalent techniques that can deal well with the design issues of communication performance, power consumption, signal integrity, and system scalability in an NoC. Finally, a novel bidirectional NoC (BiNoC) architecture with a dynamically self-reconfigurable bidirectional channel is proposed to break the conventional performance bottleneck caused by bandwidth restriction in conventional NoCs.http://dx.doi.org/10.1155/2012/509465 |
| spellingShingle | Wen-Chung Tsai Ying-Cherng Lan Yu-Hen Hu Sao-Jie Chen Networks on Chips: Structure and Design Methodologies Journal of Electrical and Computer Engineering |
| title | Networks on Chips: Structure and Design Methodologies |
| title_full | Networks on Chips: Structure and Design Methodologies |
| title_fullStr | Networks on Chips: Structure and Design Methodologies |
| title_full_unstemmed | Networks on Chips: Structure and Design Methodologies |
| title_short | Networks on Chips: Structure and Design Methodologies |
| title_sort | networks on chips structure and design methodologies |
| url | http://dx.doi.org/10.1155/2012/509465 |
| work_keys_str_mv | AT wenchungtsai networksonchipsstructureanddesignmethodologies AT yingchernglan networksonchipsstructureanddesignmethodologies AT yuhenhu networksonchipsstructureanddesignmethodologies AT saojiechen networksonchipsstructureanddesignmethodologies |