Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL
A new technique for generating true random numbers by using the ADPLL (All Digital Phase Locked Loop)-based multiple ring oscillator TRNG (MURO-TRNG) is discussed in this paper. The proposed ADPLL-based MURO-TRNG contains 10 ring oscillators, 1 conventional ADPLL, 11 sampling DFFs, 1 XOR gate, and a...
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2025-01-01
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| author | Huirem Bharat Meitei Manoj Kumar |
| author_facet | Huirem Bharat Meitei Manoj Kumar |
| author_sort | Huirem Bharat Meitei |
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| description | A new technique for generating true random numbers by using the ADPLL (All Digital Phase Locked Loop)-based multiple ring oscillator TRNG (MURO-TRNG) is discussed in this paper. The proposed ADPLL-based MURO-TRNG contains 10 ring oscillators, 1 conventional ADPLL, 11 sampling DFFs, 1 XOR gate, and an XOR corrector-based post-processing circuit. Ring oscillators are the entropy sources for the proposed MURO-TRNG architecture, and they are constructed by ADPLL with different frequencies. A new DCO(Digital Controlled Oscillator) constructed by using 9 NOR gates and 1 DFF is designed for constructing ADPLL-based ring oscillator circuits. Conventional ADPLL operates at 3 different reference frequencies to sample the raw random bits and to provide a clock for the post-processing circuit. The proposed MURO-TRNG architecture is designed using VHDL, implemented on the Artix 7, Kintex-7, and Zynq7000 FPGAs, and simulated by the Xilinx Vivado 2015.2 tool. The designed and implemented MURO-TRNG architectures consume 2-4 LUTS and 2-4 FFs. Energy consumption per bit of the generated bitstream is in the range of 4.22 nJ/bit-5.85 nJ/bit, and throughput values are in the range of 206.82 Mbps-260.07 Mbps. The NIST SP 800-22 test is conducted to validate the randomness of the generated bit stream outputs from the post-processing circuit. |
| format | Article |
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| spelling | doaj-art-84406e2412c94511940e80245da0e2b82025-01-21T00:01:28ZengIEEEIEEE Access2169-35362025-01-01139252926410.1109/ACCESS.2025.352750710835068Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLLHuirem Bharat Meitei0Manoj Kumar1https://orcid.org/0000-0001-9394-0170Department of ECE, National Institute of Technology Manipur, Imphal, Manipur, IndiaDepartment of ECE, National Institute of Technology Manipur, Imphal, Manipur, IndiaA new technique for generating true random numbers by using the ADPLL (All Digital Phase Locked Loop)-based multiple ring oscillator TRNG (MURO-TRNG) is discussed in this paper. The proposed ADPLL-based MURO-TRNG contains 10 ring oscillators, 1 conventional ADPLL, 11 sampling DFFs, 1 XOR gate, and an XOR corrector-based post-processing circuit. Ring oscillators are the entropy sources for the proposed MURO-TRNG architecture, and they are constructed by ADPLL with different frequencies. A new DCO(Digital Controlled Oscillator) constructed by using 9 NOR gates and 1 DFF is designed for constructing ADPLL-based ring oscillator circuits. Conventional ADPLL operates at 3 different reference frequencies to sample the raw random bits and to provide a clock for the post-processing circuit. The proposed MURO-TRNG architecture is designed using VHDL, implemented on the Artix 7, Kintex-7, and Zynq7000 FPGAs, and simulated by the Xilinx Vivado 2015.2 tool. The designed and implemented MURO-TRNG architectures consume 2-4 LUTS and 2-4 FFs. Energy consumption per bit of the generated bitstream is in the range of 4.22 nJ/bit-5.85 nJ/bit, and throughput values are in the range of 206.82 Mbps-260.07 Mbps. The NIST SP 800-22 test is conducted to validate the randomness of the generated bit stream outputs from the post-processing circuit.https://ieeexplore.ieee.org/document/10835068/TRNGDCOADPLLMURO-TRNGNORXOR corrector |
| spellingShingle | Huirem Bharat Meitei Manoj Kumar Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL IEEE Access TRNG DCO ADPLL MURO-TRNG NOR XOR corrector |
| title | Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL |
| title_full | Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL |
| title_fullStr | Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL |
| title_full_unstemmed | Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL |
| title_short | Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL |
| title_sort | design and implementation of multiple ring oscillator based trng architecture by using adpll |
| topic | TRNG DCO ADPLL MURO-TRNG NOR XOR corrector |
| url | https://ieeexplore.ieee.org/document/10835068/ |
| work_keys_str_mv | AT huirembharatmeitei designandimplementationofmultipleringoscillatorbasedtrngarchitecturebyusingadpll AT manojkumar designandimplementationofmultipleringoscillatorbasedtrngarchitecturebyusingadpll |