Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL
A new technique for generating true random numbers by using the ADPLL (All Digital Phase Locked Loop)-based multiple ring oscillator TRNG (MURO-TRNG) is discussed in this paper. The proposed ADPLL-based MURO-TRNG contains 10 ring oscillators, 1 conventional ADPLL, 11 sampling DFFs, 1 XOR gate, and a...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10835068/ |
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| Summary: | A new technique for generating true random numbers by using the ADPLL (All Digital Phase Locked Loop)-based multiple ring oscillator TRNG (MURO-TRNG) is discussed in this paper. The proposed ADPLL-based MURO-TRNG contains 10 ring oscillators, 1 conventional ADPLL, 11 sampling DFFs, 1 XOR gate, and an XOR corrector-based post-processing circuit. Ring oscillators are the entropy sources for the proposed MURO-TRNG architecture, and they are constructed by ADPLL with different frequencies. A new DCO(Digital Controlled Oscillator) constructed by using 9 NOR gates and 1 DFF is designed for constructing ADPLL-based ring oscillator circuits. Conventional ADPLL operates at 3 different reference frequencies to sample the raw random bits and to provide a clock for the post-processing circuit. The proposed MURO-TRNG architecture is designed using VHDL, implemented on the Artix 7, Kintex-7, and Zynq7000 FPGAs, and simulated by the Xilinx Vivado 2015.2 tool. The designed and implemented MURO-TRNG architectures consume 2-4 LUTS and 2-4 FFs. Energy consumption per bit of the generated bitstream is in the range of 4.22 nJ/bit-5.85 nJ/bit, and throughput values are in the range of 206.82 Mbps-260.07 Mbps. The NIST SP 800-22 test is conducted to validate the randomness of the generated bit stream outputs from the post-processing circuit. |
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| ISSN: | 2169-3536 |