CMOS Realization of All-Positive Pinched Hysteresis Loops
Two novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristan...
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| Format: | Article |
| Language: | English |
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Wiley
2017-01-01
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| Series: | Complexity |
| Online Access: | http://dx.doi.org/10.1155/2017/7863095 |
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| author | B. J. Maundy A. S. Elwakil C. Psychalinos |
| author_facet | B. J. Maundy A. S. Elwakil C. Psychalinos |
| author_sort | B. J. Maundy |
| collection | DOAJ |
| description | Two novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory. |
| format | Article |
| id | doaj-art-7f681ce489cc43c68bddaeaa9a9db668 |
| institution | Kabale University |
| issn | 1076-2787 1099-0526 |
| language | English |
| publishDate | 2017-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Complexity |
| spelling | doaj-art-7f681ce489cc43c68bddaeaa9a9db6682025-02-03T01:26:28ZengWileyComplexity1076-27871099-05262017-01-01201710.1155/2017/78630957863095CMOS Realization of All-Positive Pinched Hysteresis LoopsB. J. Maundy0A. S. Elwakil1C. Psychalinos2Department of Electrical and Computer Engineering, University of Calgary, Calgary, AB, T2N 1N4, CanadaDepartment of Electrical and Computer Engineering, University of Sharjah, Sharjah, UAEPhysics Department, Electronics Laboratory, University of Patras, Rio, 26504 Patras, GreeceTwo novel nonlinear circuits that exhibit an all-positive pinched hysteresis loop are proposed. These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. We show the equivalency to a charge-controlled resistance (memristance) in a decremental state via detailed analysis. Simulation and experimental results verify the proposed theory.http://dx.doi.org/10.1155/2017/7863095 |
| spellingShingle | B. J. Maundy A. S. Elwakil C. Psychalinos CMOS Realization of All-Positive Pinched Hysteresis Loops Complexity |
| title | CMOS Realization of All-Positive Pinched Hysteresis Loops |
| title_full | CMOS Realization of All-Positive Pinched Hysteresis Loops |
| title_fullStr | CMOS Realization of All-Positive Pinched Hysteresis Loops |
| title_full_unstemmed | CMOS Realization of All-Positive Pinched Hysteresis Loops |
| title_short | CMOS Realization of All-Positive Pinched Hysteresis Loops |
| title_sort | cmos realization of all positive pinched hysteresis loops |
| url | http://dx.doi.org/10.1155/2017/7863095 |
| work_keys_str_mv | AT bjmaundy cmosrealizationofallpositivepinchedhysteresisloops AT aselwakil cmosrealizationofallpositivepinchedhysteresisloops AT cpsychalinos cmosrealizationofallpositivepinchedhysteresisloops |