A High-Performance Parallel FDTD Method Enhanced by Using SSE Instruction Set
We introduce a hardware acceleration technique for the parallel finite difference time domain (FDTD) method using the SSE (streaming (single instruction multiple data) SIMD extensions) instruction set. The implementation of SSE instruction set to parallel FDTD method has achieved the significant im...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2012-01-01
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| Series: | International Journal of Antennas and Propagation |
| Online Access: | http://dx.doi.org/10.1155/2012/851465 |
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| Summary: | We introduce a hardware acceleration technique for the parallel finite difference time domain (FDTD) method using the SSE (streaming (single instruction multiple data) SIMD extensions) instruction set. The implementation of SSE instruction set to parallel FDTD method has achieved the significant improvement on the simulation performance. The benchmarks of the SSE acceleration on both the multi-CPU workstation and computer cluster have demonstrated the advantages of (vector arithmetic logic unit) VALU acceleration over GPU acceleration. Several engineering applications are employed to demonstrate the performance of parallel FDTD method enhanced by SSE instruction set. |
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| ISSN: | 1687-5869 1687-5877 |