The Potential for a GPU-Like Overlay Architecture for FPGAs

We propose a soft processor programming model and architecture inspired by graphics processing units (GPUs) that are well-matched to the strengths of FPGAs, namely, highly parallel and pipelinable computation. In particular, our soft processor architecture exploits multithreading, vector operations,...

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Main Authors: Jeffrey Kingyens, J. Gregory Steffan
Format: Article
Language:English
Published: Wiley 2011-01-01
Series:International Journal of Reconfigurable Computing
Online Access:http://dx.doi.org/10.1155/2011/514581
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author Jeffrey Kingyens
J. Gregory Steffan
author_facet Jeffrey Kingyens
J. Gregory Steffan
author_sort Jeffrey Kingyens
collection DOAJ
description We propose a soft processor programming model and architecture inspired by graphics processing units (GPUs) that are well-matched to the strengths of FPGAs, namely, highly parallel and pipelinable computation. In particular, our soft processor architecture exploits multithreading, vector operations, and predication to supply a floating-point pipeline of 64 stages via hardware support for up to 256 concurrent thread contexts. The key new contributions of our architecture are mechanisms for managing threads and register files that maximize data-level and instruction-level parallelism while overcoming the challenges of port limitations of FPGA block memories as well as memory and pipeline latency. Through simulation of a system that (i) is programmable via NVIDIA's high-level Cg language, (ii) supports AMD's CTM r5xx GPU ISA, and (iii) is realizable on an XtremeData XD1000 FPGA-based accelerator system, we demonstrate the potential for such a system to achieve 100% utilization of a deeply pipelined floating-point datapath.
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spelling doaj-art-7e44838572084841b397791a872d1d292025-02-03T01:11:30ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092011-01-01201110.1155/2011/514581514581The Potential for a GPU-Like Overlay Architecture for FPGAsJeffrey Kingyens0J. Gregory Steffan1The Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, M5S 3G4, CanadaThe Edward S. Rogers Sr. Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON, M5S 3G4, CanadaWe propose a soft processor programming model and architecture inspired by graphics processing units (GPUs) that are well-matched to the strengths of FPGAs, namely, highly parallel and pipelinable computation. In particular, our soft processor architecture exploits multithreading, vector operations, and predication to supply a floating-point pipeline of 64 stages via hardware support for up to 256 concurrent thread contexts. The key new contributions of our architecture are mechanisms for managing threads and register files that maximize data-level and instruction-level parallelism while overcoming the challenges of port limitations of FPGA block memories as well as memory and pipeline latency. Through simulation of a system that (i) is programmable via NVIDIA's high-level Cg language, (ii) supports AMD's CTM r5xx GPU ISA, and (iii) is realizable on an XtremeData XD1000 FPGA-based accelerator system, we demonstrate the potential for such a system to achieve 100% utilization of a deeply pipelined floating-point datapath.http://dx.doi.org/10.1155/2011/514581
spellingShingle Jeffrey Kingyens
J. Gregory Steffan
The Potential for a GPU-Like Overlay Architecture for FPGAs
International Journal of Reconfigurable Computing
title The Potential for a GPU-Like Overlay Architecture for FPGAs
title_full The Potential for a GPU-Like Overlay Architecture for FPGAs
title_fullStr The Potential for a GPU-Like Overlay Architecture for FPGAs
title_full_unstemmed The Potential for a GPU-Like Overlay Architecture for FPGAs
title_short The Potential for a GPU-Like Overlay Architecture for FPGAs
title_sort potential for a gpu like overlay architecture for fpgas
url http://dx.doi.org/10.1155/2011/514581
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