Implementing Cyclic Redundancy Check as Error Correction Technique in HDLC
Saved in:
| Main Authors: | Shardeep Kaur Sooch, Meenu Gupta, Rakesh Kumar |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Polish Information Processing Society
2020-01-01
|
| Series: | Annals of computer science and information systems |
| Online Access: | https://annals-csis.org/Volume_24/drp/pdf/13.pdf |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Automatic Recognition and Replacement of Cyclic Redundancy Checks for Program Optimization
by: Mariam Arutunian, et al.
Published: (2024-01-01) -
A cyclic redundancy check aided encoding construction method for list sphere polar decoder
by: Wenbin Hu, et al.
Published: (2025-08-01) -
The Prognostic Significance of the DBIL/HDLC Ratio in Patients With Dilated Cardiomyopathy
by: Xinyi Wang, et al.
Published: (2025-01-01) -
Design and verification of HDLC data frame parallel search and decapsulation module
by: Qian Yong, et al.
Published: (2022-01-01) -
Design of Communication Gateway Between HDLC and RS485 Based on FPGA
by: 李成钢, et al.
Published: (2011-01-01)