Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique
This paper reports a wideband blocker-tolerant receiver (RX) that covers a 0.5-to-2 GHz radio frequency (RF) range. By combining the gain-boosted (GB) mixer-first low-noise amplifier (LNA) network with a bottom-plate switched-capacitor (SC) N-path filter, the proposed RX provides a high RF gain and...
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| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of Circuits and Systems |
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| Online Access: | https://ieeexplore.ieee.org/document/10500899/ |
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| author | Yi Mao Gengzhen Qi Pui-In Mak |
| author_facet | Yi Mao Gengzhen Qi Pui-In Mak |
| author_sort | Yi Mao |
| collection | DOAJ |
| description | This paper reports a wideband blocker-tolerant receiver (RX) that covers a 0.5-to-2 GHz radio frequency (RF) range. By combining the gain-boosted (GB) mixer-first low-noise amplifier (LNA) network with a bottom-plate switched-capacitor (SC) N-path filter, the proposed RX provides a high RF gain and high out-of-band (OOB) blocker suppression to improve both the noise figure (NF) and OOB linearity. Particularly, our RX features enhanced filtering at the input side that can effectively prevent the OOB blockers from entering into the RX. By deriving its linear time-invariant (LTI) model, the input impedance matching, gain response and noise performance are analyzed. Besides that, a clock-delay technique is proposed to improve the LO non-overlap characteristics. Designed in 65-nm CMOS, the simulated results present that under an 80-MHz offset frequency, the RX scores a 29 dBm OOB-IIP3 and a -2.3 dBm B-1dB. The NF ranges between 3.2 to 6 dB, and the active area is 0.66 mm 2. At 2 GHz, the power consumption is 25 mW, of which only 4.7 mW is due to the LO dynamic power. |
| format | Article |
| id | doaj-art-78aeca8e621f46cfa8949b6ba93e6175 |
| institution | Kabale University |
| issn | 2644-1225 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Circuits and Systems |
| spelling | doaj-art-78aeca8e621f46cfa8949b6ba93e61752025-01-21T00:02:43ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252024-01-0159210110.1109/OJCAS.2023.333511610500899Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor TechniqueYi Mao0Gengzhen Qi1https://orcid.org/0000-0001-5035-8017Pui-In Mak2https://orcid.org/0000-0002-3579-8740School of Microelectronics Science and Technology, Sun Yat-sen University, Guangdong, ChinaSchool of Microelectronics Science and Technology, Sun Yat-sen University, Guangdong, ChinaState-Key Laboratory of Analog and Mixed-Signal VLSI/IME, University of Macau, Macau, ChinaThis paper reports a wideband blocker-tolerant receiver (RX) that covers a 0.5-to-2 GHz radio frequency (RF) range. By combining the gain-boosted (GB) mixer-first low-noise amplifier (LNA) network with a bottom-plate switched-capacitor (SC) N-path filter, the proposed RX provides a high RF gain and high out-of-band (OOB) blocker suppression to improve both the noise figure (NF) and OOB linearity. Particularly, our RX features enhanced filtering at the input side that can effectively prevent the OOB blockers from entering into the RX. By deriving its linear time-invariant (LTI) model, the input impedance matching, gain response and noise performance are analyzed. Besides that, a clock-delay technique is proposed to improve the LO non-overlap characteristics. Designed in 65-nm CMOS, the simulated results present that under an 80-MHz offset frequency, the RX scores a 29 dBm OOB-IIP3 and a -2.3 dBm B-1dB. The NF ranges between 3.2 to 6 dB, and the active area is 0.66 mm 2. At 2 GHz, the power consumption is 25 mW, of which only 4.7 mW is due to the LO dynamic power.https://ieeexplore.ieee.org/document/10500899/linearitylow-noise amplifier (LNA)LO generatorN-path filterOOB-IIP₃noise figure (NF) |
| spellingShingle | Yi Mao Gengzhen Qi Pui-In Mak Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique IEEE Open Journal of Circuits and Systems linearity low-noise amplifier (LNA) LO generator N-path filter OOB-IIP₃ noise figure (NF) |
| title | Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique |
| title_full | Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique |
| title_fullStr | Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique |
| title_full_unstemmed | Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique |
| title_short | Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique |
| title_sort | design and analysis of a blocker tolerant gain boosted n path receiver using a bottom plate switched capacitor technique |
| topic | linearity low-noise amplifier (LNA) LO generator N-path filter OOB-IIP₃ noise figure (NF) |
| url | https://ieeexplore.ieee.org/document/10500899/ |
| work_keys_str_mv | AT yimao designandanalysisofablockertolerantgainboostednpathreceiverusingabottomplateswitchedcapacitortechnique AT gengzhenqi designandanalysisofablockertolerantgainboostednpathreceiverusingabottomplateswitchedcapacitortechnique AT puiinmak designandanalysisofablockertolerantgainboostednpathreceiverusingabottomplateswitchedcapacitortechnique |