Analysis and Simulation of Functional Stress Degradation on VDOMS Power Transistors
The use of VDMOS transistor under certain functional stress conditions produces a modification of its physical and electrical properties. This paper explores the physical analysis and SPICE simulation of the degradation effects related to the component micronic structure, and points out the degraded...
Saved in:
Main Authors: | M. Zoaeter, B. Beydoun, M. Hajjar, M. Debs, J-P Charles |
---|---|
Format: | Article |
Language: | English |
Published: |
Wiley
2002-01-01
|
Series: | Active and Passive Electronic Components |
Online Access: | http://dx.doi.org/10.1080/08827510213500 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Relaxable Damage in Hot-Carrier Stressing of n-MOS Transistors
by: M. Rahmoun, et al.
Published: (2000-01-01) -
Analysis of Hot-Carrier Degradation in Small and Large W/L n-Channel Transistors
by: E. Bendada, et al.
Published: (1998-01-01) -
High Speed Non-Linear Circuit
Simulation of Bipolar Junction
Transistors
by: M. N. Doja, et al.
Published: (1999-01-01) -
Recovery Analysis of Sequentially Irradiated and NBT-Stressed VDMOS Transistors
by: Snežana Djorić-Veljković, et al.
Published: (2024-12-01) -
Low-power artificial neuron networks with enhanced synaptic functionality using dual transistor and dual memristor.
by: Keerthi Nalliboyina, et al.
Published: (2025-01-01)