Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices
Abstract Memristors are two‐terminal nano‐electronic devices that make it possible to design non‐volatile memory and logic circuits with high integration density. The logic operations of memristor‐based circuits are performed by applying suitable voltages across them. Researchers have been widely ex...
Saved in:
| Main Authors: | , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2021-03-01
|
| Series: | IET Computers & Digital Techniques |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cdt2.12007 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832558664655831040 |
|---|---|
| author | Anindita Chakraborty Vivek Maurya Sneha Prasad Suryansh Gupta Rajat Subhra Chakraborty Hafizur Rahaman |
| author_facet | Anindita Chakraborty Vivek Maurya Sneha Prasad Suryansh Gupta Rajat Subhra Chakraborty Hafizur Rahaman |
| author_sort | Anindita Chakraborty |
| collection | DOAJ |
| description | Abstract Memristors are two‐terminal nano‐electronic devices that make it possible to design non‐volatile memory and logic circuits with high integration density. The logic operations of memristor‐based circuits are performed by applying suitable voltages across them. Researchers have been widely experimenting with this device to efficiently implement particular logic functions. However, recently, a synthesis methodology for arbitrary logic functions has been reported, where an input Boolean function is first represented as a Binary Decision Diagram (BDD), followed by the mapping of the BDD‐nodes (netlists of 2‐input NOR and NOT gates) inside a cluster of sliced crossbar‐arrays. The authors propose to map the BDD‐nodes for any input Boolean function to the crossbar‐slices using an improved technique, where each BDD‐node is mapped more efficiently, and the node‐logic is implemented following the Memristor Aided loGIC (MAGIC) design style. Our proposed mapping‐based realization of a BDD‐node has superior performance and energy‐efficiency than the existing IMPLY and MAGIC‐based BDD‐node designs techniques, provided all three node‐designs are implemented inside the similar‐sized crossbars. Comparative‐study of the synthesis results showed that the memristive‐circuits generated using our proposed technique are 26.95% faster, and need 42.32% lesser memristors (on average) than their peers, implemented using the existing approach of slicing crossbar‐architecture. |
| format | Article |
| id | doaj-art-757eac7efd8b47e39f2b981b9e778b32 |
| institution | Kabale University |
| issn | 1751-8601 1751-861X |
| language | English |
| publishDate | 2021-03-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Computers & Digital Techniques |
| spelling | doaj-art-757eac7efd8b47e39f2b981b9e778b322025-02-03T01:31:55ZengWileyIET Computers & Digital Techniques1751-86011751-861X2021-03-0115211212410.1049/cdt2.12007Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slicesAnindita Chakraborty0Vivek Maurya1Sneha Prasad2Suryansh Gupta3Rajat Subhra Chakraborty4Hafizur Rahaman5Indian Institute of Engineering Science and Technology Shibpur IndiaIndian Institute of Engineering Science and Technology Shibpur IndiaIndian Institute of Engineering Science and Technology Shibpur IndiaIndian Institute of Engineering Science and Technology Shibpur IndiaIndian Institute of Technology Kharagpur IndiaIndian Institute of Engineering Science and Technology Shibpur IndiaAbstract Memristors are two‐terminal nano‐electronic devices that make it possible to design non‐volatile memory and logic circuits with high integration density. The logic operations of memristor‐based circuits are performed by applying suitable voltages across them. Researchers have been widely experimenting with this device to efficiently implement particular logic functions. However, recently, a synthesis methodology for arbitrary logic functions has been reported, where an input Boolean function is first represented as a Binary Decision Diagram (BDD), followed by the mapping of the BDD‐nodes (netlists of 2‐input NOR and NOT gates) inside a cluster of sliced crossbar‐arrays. The authors propose to map the BDD‐nodes for any input Boolean function to the crossbar‐slices using an improved technique, where each BDD‐node is mapped more efficiently, and the node‐logic is implemented following the Memristor Aided loGIC (MAGIC) design style. Our proposed mapping‐based realization of a BDD‐node has superior performance and energy‐efficiency than the existing IMPLY and MAGIC‐based BDD‐node designs techniques, provided all three node‐designs are implemented inside the similar‐sized crossbars. Comparative‐study of the synthesis results showed that the memristive‐circuits generated using our proposed technique are 26.95% faster, and need 42.32% lesser memristors (on average) than their peers, implemented using the existing approach of slicing crossbar‐architecture.https://doi.org/10.1049/cdt2.12007binary decision diagramsBoolean functionslogic circuitslogic designlogic gatesnanoelectronics |
| spellingShingle | Anindita Chakraborty Vivek Maurya Sneha Prasad Suryansh Gupta Rajat Subhra Chakraborty Hafizur Rahaman Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices IET Computers & Digital Techniques binary decision diagrams Boolean functions logic circuits logic design logic gates nanoelectronics |
| title | Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices |
| title_full | Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices |
| title_fullStr | Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices |
| title_full_unstemmed | Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices |
| title_short | Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices |
| title_sort | binary decision diagram based synthesis technique for improved mapping of boolean functions inside memristive crossbar slices |
| topic | binary decision diagrams Boolean functions logic circuits logic design logic gates nanoelectronics |
| url | https://doi.org/10.1049/cdt2.12007 |
| work_keys_str_mv | AT aninditachakraborty binarydecisiondiagrambasedsynthesistechniqueforimprovedmappingofbooleanfunctionsinsidememristivecrossbarslices AT vivekmaurya binarydecisiondiagrambasedsynthesistechniqueforimprovedmappingofbooleanfunctionsinsidememristivecrossbarslices AT snehaprasad binarydecisiondiagrambasedsynthesistechniqueforimprovedmappingofbooleanfunctionsinsidememristivecrossbarslices AT suryanshgupta binarydecisiondiagrambasedsynthesistechniqueforimprovedmappingofbooleanfunctionsinsidememristivecrossbarslices AT rajatsubhrachakraborty binarydecisiondiagrambasedsynthesistechniqueforimprovedmappingofbooleanfunctionsinsidememristivecrossbarslices AT hafizurrahaman binarydecisiondiagrambasedsynthesistechniqueforimprovedmappingofbooleanfunctionsinsidememristivecrossbarslices |