Current mirror with charge dissipation transistor for analogue single‐event transient mitigation in space application
Abstract Current mirror utilizing an extra transistor for single‐event‐induced charge dissipation is proposed. This technique involves two inverters and a dissipation transistor. The inverters are employed as a sensor that turns on the dissipation transistor when heavy ion hits the sensitive node, a...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2021-03-01
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| Series: | IET Circuits, Devices and Systems |
| Online Access: | https://doi.org/10.1049/cds2.12012 |
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| _version_ | 1832559630902886400 |
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| author | Jingtian Liu Bin Liang Jianjun Chen Yaqing Chi Li Yan Yang Guo |
| author_facet | Jingtian Liu Bin Liang Jianjun Chen Yaqing Chi Li Yan Yang Guo |
| author_sort | Jingtian Liu |
| collection | DOAJ |
| description | Abstract Current mirror utilizing an extra transistor for single‐event‐induced charge dissipation is proposed. This technique involves two inverters and a dissipation transistor. The inverters are employed as a sensor that turns on the dissipation transistor when heavy ion hits the sensitive node, and the dissipation transistor helps to attenuate the single‐event transient (SET)‐induced perturbation. During normal operation, inverters are in static state, and the dissipation transistor is off, which has no effect on circuit performance, and contributes to negligible power consumption. Once heavy ion strikes the sensitive node and the fault is detected, the dissipation transistor is triggered to self‐correct the SET disturbance. Simulation results indicate that the proposed technique reduces the SET pulse duration by at least 48.4% with linear energy transfers of 30 MeV cm2/mg. This paper provides a novel hardening method for analogue single‐event transient mitigation in current mirror circuits. |
| format | Article |
| id | doaj-art-756fd1ece84d48909408da980c83f892 |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2021-03-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-756fd1ece84d48909408da980c83f8922025-02-03T01:29:39ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982021-03-0115213614010.1049/cds2.12012Current mirror with charge dissipation transistor for analogue single‐event transient mitigation in space applicationJingtian Liu0Bin Liang1Jianjun Chen2Yaqing Chi3Li Yan4Yang Guo5School of Computer Science National University of Defense Technology Changsha ChinaSchool of Computer Science National University of Defense Technology Changsha ChinaSchool of Computer Science National University of Defense Technology Changsha ChinaSchool of Computer Science National University of Defense Technology Changsha ChinaSchool of Computer Science National University of Defense Technology Changsha ChinaSchool of Computer Science National University of Defense Technology Changsha ChinaAbstract Current mirror utilizing an extra transistor for single‐event‐induced charge dissipation is proposed. This technique involves two inverters and a dissipation transistor. The inverters are employed as a sensor that turns on the dissipation transistor when heavy ion hits the sensitive node, and the dissipation transistor helps to attenuate the single‐event transient (SET)‐induced perturbation. During normal operation, inverters are in static state, and the dissipation transistor is off, which has no effect on circuit performance, and contributes to negligible power consumption. Once heavy ion strikes the sensitive node and the fault is detected, the dissipation transistor is triggered to self‐correct the SET disturbance. Simulation results indicate that the proposed technique reduces the SET pulse duration by at least 48.4% with linear energy transfers of 30 MeV cm2/mg. This paper provides a novel hardening method for analogue single‐event transient mitigation in current mirror circuits.https://doi.org/10.1049/cds2.12012 |
| spellingShingle | Jingtian Liu Bin Liang Jianjun Chen Yaqing Chi Li Yan Yang Guo Current mirror with charge dissipation transistor for analogue single‐event transient mitigation in space application IET Circuits, Devices and Systems |
| title | Current mirror with charge dissipation transistor for analogue single‐event transient mitigation in space application |
| title_full | Current mirror with charge dissipation transistor for analogue single‐event transient mitigation in space application |
| title_fullStr | Current mirror with charge dissipation transistor for analogue single‐event transient mitigation in space application |
| title_full_unstemmed | Current mirror with charge dissipation transistor for analogue single‐event transient mitigation in space application |
| title_short | Current mirror with charge dissipation transistor for analogue single‐event transient mitigation in space application |
| title_sort | current mirror with charge dissipation transistor for analogue single event transient mitigation in space application |
| url | https://doi.org/10.1049/cds2.12012 |
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