Technology and Modeling of Nonclassical Transistor Devices
This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of tr...
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| Format: | Article |
| Language: | English |
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Wiley
2019-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2019/4792461 |
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| author | George V. Angelov Dimitar N. Nikolov Marin H. Hristov |
| author_facet | George V. Angelov Dimitar N. Nikolov Marin H. Hristov |
| author_sort | George V. Angelov |
| collection | DOAJ |
| description | This paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed. |
| format | Article |
| id | doaj-art-743c4b62172448c1a5183b1a5c4cf592 |
| institution | Kabale University |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2019-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-743c4b62172448c1a5183b1a5c4cf5922025-02-03T05:52:47ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552019-01-01201910.1155/2019/47924614792461Technology and Modeling of Nonclassical Transistor DevicesGeorge V. Angelov0Dimitar N. Nikolov1Marin H. Hristov2Department of Microelectronics, FETT, Technical University of Sofia, 1756 Sofia, BulgariaDepartment of Electronics, FETT, Technical University of Sofia, 1756 Sofia, BulgariaDepartment of Microelectronics, FETT, Technical University of Sofia, 1756 Sofia, BulgariaThis paper presents a comprehensive outlook for the current technology status and the prospective upcoming advancements. VLSI scaling trends and technology advancements in the context of sub-10-nm technologies are reviewed as well as the associated device modeling approaches and compact models of transistor structures are considered. As technology goes into the nanometer regime, semiconductor devices are confronting numerous short-channel effects. Bulk CMOS technology is developing and innovating to overcome these constraints by introduction of (i) new technologies and new materials and (ii) new transistor architectures. Technology boosters such as high-k/metal-gate technologies, ultra-thin-body SOI, Ge-on-insulator (GOI), AIII–BV semiconductors, and band-engineered transistor (SiGe or Strained Si-channel) with high-carrier-mobility channels are examined. Nonclassical device structures such as novel multiple-gate transistor structures including multiple-gate field-effect transistors, FD-SOI MOSFETs, CNTFETs, and SETs are examined as possible successors of conventional CMOS devices and FinFETs. Special attention is devoted to gate-all-around FETs and, respectively, nanowire and nanosheet FETs as forthcoming mainstream replacements of FinFET. In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.http://dx.doi.org/10.1155/2019/4792461 |
| spellingShingle | George V. Angelov Dimitar N. Nikolov Marin H. Hristov Technology and Modeling of Nonclassical Transistor Devices Journal of Electrical and Computer Engineering |
| title | Technology and Modeling of Nonclassical Transistor Devices |
| title_full | Technology and Modeling of Nonclassical Transistor Devices |
| title_fullStr | Technology and Modeling of Nonclassical Transistor Devices |
| title_full_unstemmed | Technology and Modeling of Nonclassical Transistor Devices |
| title_short | Technology and Modeling of Nonclassical Transistor Devices |
| title_sort | technology and modeling of nonclassical transistor devices |
| url | http://dx.doi.org/10.1155/2019/4792461 |
| work_keys_str_mv | AT georgevangelov technologyandmodelingofnonclassicaltransistordevices AT dimitarnnikolov technologyandmodelingofnonclassicaltransistordevices AT marinhhristov technologyandmodelingofnonclassicaltransistordevices |