Analysis of power–accuracy trade‐off in digital signal processing applications using low‐power approximate adders - Celia Dharmaraj; Vinita Vasudevan; Nitin Chandrachoodan (IET Computers & Digital Techniques)
Abstract In recent years, approximate circuit design targeting the error‐tolerant applications has gained significance. In this study, the authors propose a metric that ranks a stand‐alone approximate adder in terms of power savings obtained for a given mean error distance/mean square error (MSE). The authors demonstrate that this ranking of approximate adders can be used in applications that contain adder trees and registers. In applications that also have accurate multipliers interspersed with adders, the authors find that certain types of approximations in the adders result in more power‐efficient implementations of multipliers. Besides power savings, the other metrics of interest are noise floor and mean error in filtering applications and the compression achieved for a given peak signal‐to‐noise ratio (PSNR) in image compression applications. The authors also show that for the same overall MSE, there is a trade‐off between noise floor and mean error. This makes it possible to classify these adders based on whether they result in an increased noise floor or a mean error for the same overall MSE. Furthermore, the authors discuss the effect of using an approximate discrete cosine transform block to meet the reduced PSNR requirements, on the overall compression levels and the trade‐offs involved in the process.