A Dynamic Dual Fixed-Point Arithmetic Architecture for FPGAs
In FPGA embedded systems, designers usually have to make a compromise between numerical precision and logical resources. Scientific computations in particular, usually require highly accurate calculations and are computing intensive. In this context, a designer is left with the task of implementing...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2011-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2011/518602 |
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| Summary: | In FPGA embedded systems, designers usually have to make a compromise between numerical precision and logical resources. Scientific computations in particular, usually require
highly accurate calculations and are computing intensive. In this context, a designer is left with the task of implementing several
arithmetic cores for parallel processing while supporting high numerical precision with finite logical resources.
This paper introduces an arithmetic architecture that uses runtime partial reconfiguration to dynamically adapt its numerical
precision, without requiring significant additional logical resources. The paper also quantifies the relationship between
reduced logical resources and savings in power consumption, which is particularly important for FPGA implementations. Finally, our results show performance benefits when this approach is compared to alternative static solutions within bounds on the reconfiguration rate. |
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| ISSN: | 1687-7195 1687-7209 |