A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing
This work presents a small-area 2nd-order continuous-time <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> Modulator (CT<inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma \text{M}$ </tex-math&...
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| Format: | Article |
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of Circuits and Systems |
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| Online Access: | https://ieeexplore.ieee.org/document/10475189/ |
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| author | Manish Srivastava Alessandro Ferro Aleksandr Sidun Jose M. De La Rosa Kilian O'Donoghue Padraig Cantillon-Murphy Daniel O'Hare |
| author_facet | Manish Srivastava Alessandro Ferro Aleksandr Sidun Jose M. De La Rosa Kilian O'Donoghue Padraig Cantillon-Murphy Daniel O'Hare |
| author_sort | Manish Srivastava |
| collection | DOAJ |
| description | This work presents a small-area 2nd-order continuous-time <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> Modulator (CT<inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma \text{M}$ </tex-math></inline-formula>) with a single low dropout regulator (LDO) serving as both the power supply for the CT<inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma \text{M}$ </tex-math></inline-formula> and reference voltage buffer. The CT<inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma \text{M}$ </tex-math></inline-formula> is used for digitising very low amplitude signals in applications such as magnetic tracking for image-guided and robotic surgery. A cascade of integrators in a feed-forward architecture implemented with an adder-less architecture has been proposed to minimise the silicon area. In addition, a novel continuous-time pulse-shaped digital-to-analog converter (CT-PS DAC) is proposed for excess loop delay (ELD) compensation to simplify the current drive requirements of the reference voltage buffer. This enables a single low-dropout (LDO) voltage regulator to generate both power supply and <inline-formula> <tex-math notation="LaTeX">$\text{V}_{ref}$ </tex-math></inline-formula> for the DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and 91-dB DR within a signal bandwidth of 20 kHz and the CT<inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma \text{M}$ </tex-math></inline-formula> consumes <inline-formula> <tex-math notation="LaTeX">$300 ~\mu \text{W}$ </tex-math></inline-formula> of power when clocked at 10.24 MHz. The CT<inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma \text{M}$ </tex-math></inline-formula> achieves a state-of-the-art area of 0.07 mm2. |
| format | Article |
| id | doaj-art-6c8e6d802a7e4d09bb7f2c65bbc2d45c |
| institution | Kabale University |
| issn | 2644-1225 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Circuits and Systems |
| spelling | doaj-art-6c8e6d802a7e4d09bb7f2c65bbc2d45c2025-01-21T00:02:44ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252024-01-015425410.1109/OJCAS.2024.337865310475189A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic SensingManish Srivastava0https://orcid.org/0000-0001-5370-3787Alessandro Ferro1https://orcid.org/0009-0009-5542-1842Aleksandr Sidun2Jose M. De La Rosa3https://orcid.org/0000-0003-2848-9226Kilian O'Donoghue4Padraig Cantillon-Murphy5https://orcid.org/0000-0001-6679-2889Daniel O'Hare6https://orcid.org/0000-0002-2919-1301MCCI, Tyndall National Institute, University College Cork, Cork, IrelandMCCI, Tyndall National Institute, University College Cork, Cork, IrelandMCCI, Tyndall National Institute, University College Cork, Cork, IrelandInstituto de Microelectronica de Sevilla, IMSE-CNM (CSIC/Universidad de Sevilla), Seville, SpainMCCI, Tyndall National Institute, University College Cork, Cork, IrelandMCCI, Tyndall National Institute, University College Cork, Cork, IrelandMCCI, Tyndall National Institute, University College Cork, Cork, IrelandThis work presents a small-area 2nd-order continuous-time <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula> Modulator (CT<inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma \text{M}$ </tex-math></inline-formula>) with a single low dropout regulator (LDO) serving as both the power supply for the CT<inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma \text{M}$ </tex-math></inline-formula> and reference voltage buffer. The CT<inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma \text{M}$ </tex-math></inline-formula> is used for digitising very low amplitude signals in applications such as magnetic tracking for image-guided and robotic surgery. A cascade of integrators in a feed-forward architecture implemented with an adder-less architecture has been proposed to minimise the silicon area. In addition, a novel continuous-time pulse-shaped digital-to-analog converter (CT-PS DAC) is proposed for excess loop delay (ELD) compensation to simplify the current drive requirements of the reference voltage buffer. This enables a single low-dropout (LDO) voltage regulator to generate both power supply and <inline-formula> <tex-math notation="LaTeX">$\text{V}_{ref}$ </tex-math></inline-formula> for the DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and 91-dB DR within a signal bandwidth of 20 kHz and the CT<inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma \text{M}$ </tex-math></inline-formula> consumes <inline-formula> <tex-math notation="LaTeX">$300 ~\mu \text{W}$ </tex-math></inline-formula> of power when clocked at 10.24 MHz. The CT<inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma \text{M}$ </tex-math></inline-formula> achieves a state-of-the-art area of 0.07 mm2.https://ieeexplore.ieee.org/document/10475189/Analog-to-digital conversioncontinuous-time delta-sigma modulationexcess loop-delay compensationFIR DACmagnetic sensorsensor interface |
| spellingShingle | Manish Srivastava Alessandro Ferro Aleksandr Sidun Jose M. De La Rosa Kilian O'Donoghue Padraig Cantillon-Murphy Daniel O'Hare A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing IEEE Open Journal of Circuits and Systems Analog-to-digital conversion continuous-time delta-sigma modulation excess loop-delay compensation FIR DAC magnetic sensor sensor interface |
| title | A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing |
| title_full | A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing |
| title_fullStr | A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing |
| title_full_unstemmed | A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing |
| title_short | A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing |
| title_sort | small area 2nd order adder less continuous time x0394 x03a3 modulator with pulse shaping fir dac for magnetic sensing |
| topic | Analog-to-digital conversion continuous-time delta-sigma modulation excess loop-delay compensation FIR DAC magnetic sensor sensor interface |
| url | https://ieeexplore.ieee.org/document/10475189/ |
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