Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique
Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An ef...
Saved in:
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
Wiley
2015-01-01
|
| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2015/570836 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832564335841378304 |
|---|---|
| author | Alireza Monemi Chia Yee Ooi Muhammad Nadzir Marsono |
| author_facet | Alireza Monemi Chia Yee Ooi Muhammad Nadzir Marsono |
| author_sort | Alireza Monemi |
| collection | DOAJ |
| description | Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%~20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT. |
| format | Article |
| id | doaj-art-6c5c95d9c17c47e9bf6ac1cfd051c699 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2015-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-6c5c95d9c17c47e9bf6ac1cfd051c6992025-02-03T01:11:16ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092015-01-01201510.1155/2015/570836570836Low Latency Network-on-Chip Router Microarchitecture Using Request Masking TechniqueAlireza Monemi0Chia Yee Ooi1Muhammad Nadzir Marsono2Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Johor Bahru, MalaysiaMalaysia-Japan International Institute of Technology (MJIIT), Universiti Teknologi Malaysia, 54100 Kuala Lumpur, MalaysiaFaculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Johor Bahru, MalaysiaNetwork-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%~20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.http://dx.doi.org/10.1155/2015/570836 |
| spellingShingle | Alireza Monemi Chia Yee Ooi Muhammad Nadzir Marsono Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique International Journal of Reconfigurable Computing |
| title | Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique |
| title_full | Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique |
| title_fullStr | Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique |
| title_full_unstemmed | Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique |
| title_short | Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique |
| title_sort | low latency network on chip router microarchitecture using request masking technique |
| url | http://dx.doi.org/10.1155/2015/570836 |
| work_keys_str_mv | AT alirezamonemi lowlatencynetworkonchiproutermicroarchitectureusingrequestmaskingtechnique AT chiayeeooi lowlatencynetworkonchiproutermicroarchitectureusingrequestmaskingtechnique AT muhammadnadzirmarsono lowlatencynetworkonchiproutermicroarchitectureusingrequestmaskingtechnique |