FPGA-Based Distributed Union-Find Decoder for Surface Codes
A fault-tolerant quantum computer must decode and correct errors faster than they appear to prevent exponential slowdown due to error correction. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than <inline-formula><tex-math notation="LaTeX"...
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IEEE
2024-01-01
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| Series: | IEEE Transactions on Quantum Engineering |
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| Online Access: | https://ieeexplore.ieee.org/document/10693533/ |
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| author | Namitha Liyanage Yue Wu Siona Tagare Lin Zhong |
| author_facet | Namitha Liyanage Yue Wu Siona Tagare Lin Zhong |
| author_sort | Namitha Liyanage |
| collection | DOAJ |
| description | A fault-tolerant quantum computer must decode and correct errors faster than they appear to prevent exponential slowdown due to error correction. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than <inline-formula><tex-math notation="LaTeX">$O(d^{3})$</tex-math></inline-formula>. We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using a field-programmable gate array (FPGA)-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to <inline-formula><tex-math notation="LaTeX">$d$</tex-math></inline-formula>, given <inline-formula><tex-math notation="LaTeX">$O(d^{3})$</tex-math></inline-formula> parallel computing resources. The decoding time per measurement round decreases as <inline-formula><tex-math notation="LaTeX">$d$</tex-math></inline-formula> increases, the first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. Using a Xilinx VCU129 FPGA, we successfully implement <inline-formula><tex-math notation="LaTeX">$d$</tex-math></inline-formula> up to 21 with an average decoding time of 11.5 ns per measurement round under 0.1% phenomenological noise and 23.7 ns for <inline-formula><tex-math notation="LaTeX">$d=17$</tex-math></inline-formula> under equivalent circuit-level noise. This performance is significantly faster than any existing decoder implementation. Furthermore, we show that Helios can optimize for resource efficiency by decoding <inline-formula><tex-math notation="LaTeX">$d=51$</tex-math></inline-formula> on a Xilinx VCU129 FPGA with an average latency of 544 ns per measurement round. |
| format | Article |
| id | doaj-art-6ae54de00d2d4a5899d444241cfecc1d |
| institution | Kabale University |
| issn | 2689-1808 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Transactions on Quantum Engineering |
| spelling | doaj-art-6ae54de00d2d4a5899d444241cfecc1d2025-01-25T00:03:48ZengIEEEIEEE Transactions on Quantum Engineering2689-18082024-01-01511810.1109/TQE.2024.346727110693533FPGA-Based Distributed Union-Find Decoder for Surface CodesNamitha Liyanage0https://orcid.org/0009-0003-7075-9071Yue Wu1Siona Tagare2https://orcid.org/0009-0005-1510-4843Lin Zhong3Department of Computer Science, Yale University, New Haven, CT, USADepartment of Computer Science, Yale University, New Haven, CT, USADepartment of Computer Science, Yale University, New Haven, CT, USADepartment of Computer Science, Yale University, New Haven, CT, USAA fault-tolerant quantum computer must decode and correct errors faster than they appear to prevent exponential slowdown due to error correction. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than <inline-formula><tex-math notation="LaTeX">$O(d^{3})$</tex-math></inline-formula>. We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using a field-programmable gate array (FPGA)-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to <inline-formula><tex-math notation="LaTeX">$d$</tex-math></inline-formula>, given <inline-formula><tex-math notation="LaTeX">$O(d^{3})$</tex-math></inline-formula> parallel computing resources. The decoding time per measurement round decreases as <inline-formula><tex-math notation="LaTeX">$d$</tex-math></inline-formula> increases, the first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. Using a Xilinx VCU129 FPGA, we successfully implement <inline-formula><tex-math notation="LaTeX">$d$</tex-math></inline-formula> up to 21 with an average decoding time of 11.5 ns per measurement round under 0.1% phenomenological noise and 23.7 ns for <inline-formula><tex-math notation="LaTeX">$d=17$</tex-math></inline-formula> under equivalent circuit-level noise. This performance is significantly faster than any existing decoder implementation. Furthermore, we show that Helios can optimize for resource efficiency by decoding <inline-formula><tex-math notation="LaTeX">$d=51$</tex-math></inline-formula> on a Xilinx VCU129 FPGA with an average latency of 544 ns per measurement round.https://ieeexplore.ieee.org/document/10693533/Field-programmable gate array (FPGA)quantum error correction (QEC)surface codesUnion-Find (UF) |
| spellingShingle | Namitha Liyanage Yue Wu Siona Tagare Lin Zhong FPGA-Based Distributed Union-Find Decoder for Surface Codes IEEE Transactions on Quantum Engineering Field-programmable gate array (FPGA) quantum error correction (QEC) surface codes Union-Find (UF) |
| title | FPGA-Based Distributed Union-Find Decoder for Surface Codes |
| title_full | FPGA-Based Distributed Union-Find Decoder for Surface Codes |
| title_fullStr | FPGA-Based Distributed Union-Find Decoder for Surface Codes |
| title_full_unstemmed | FPGA-Based Distributed Union-Find Decoder for Surface Codes |
| title_short | FPGA-Based Distributed Union-Find Decoder for Surface Codes |
| title_sort | fpga based distributed union find decoder for surface codes |
| topic | Field-programmable gate array (FPGA) quantum error correction (QEC) surface codes Union-Find (UF) |
| url | https://ieeexplore.ieee.org/document/10693533/ |
| work_keys_str_mv | AT namithaliyanage fpgabaseddistributedunionfinddecoderforsurfacecodes AT yuewu fpgabaseddistributedunionfinddecoderforsurfacecodes AT sionatagare fpgabaseddistributedunionfinddecoderforsurfacecodes AT linzhong fpgabaseddistributedunionfinddecoderforsurfacecodes |