FPGA-Based Distributed Union-Find Decoder for Surface Codes
A fault-tolerant quantum computer must decode and correct errors faster than they appear to prevent exponential slowdown due to error correction. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than <inline-formula><tex-math notation="LaTeX"...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2024-01-01
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| Series: | IEEE Transactions on Quantum Engineering |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10693533/ |
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| Summary: | A fault-tolerant quantum computer must decode and correct errors faster than they appear to prevent exponential slowdown due to error correction. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than <inline-formula><tex-math notation="LaTeX">$O(d^{3})$</tex-math></inline-formula>. We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using a field-programmable gate array (FPGA)-based implementation, we empirically show that this distributed UF decoder has a sublinear average time complexity with regard to <inline-formula><tex-math notation="LaTeX">$d$</tex-math></inline-formula>, given <inline-formula><tex-math notation="LaTeX">$O(d^{3})$</tex-math></inline-formula> parallel computing resources. The decoding time per measurement round decreases as <inline-formula><tex-math notation="LaTeX">$d$</tex-math></inline-formula> increases, the first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. Using a Xilinx VCU129 FPGA, we successfully implement <inline-formula><tex-math notation="LaTeX">$d$</tex-math></inline-formula> up to 21 with an average decoding time of 11.5 ns per measurement round under 0.1% phenomenological noise and 23.7 ns for <inline-formula><tex-math notation="LaTeX">$d=17$</tex-math></inline-formula> under equivalent circuit-level noise. This performance is significantly faster than any existing decoder implementation. Furthermore, we show that Helios can optimize for resource efficiency by decoding <inline-formula><tex-math notation="LaTeX">$d=51$</tex-math></inline-formula> on a Xilinx VCU129 FPGA with an average latency of 544 ns per measurement round. |
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| ISSN: | 2689-1808 |