Exploration of Heterogeneous FPGA Architectures
Mesh-based heterogeneous FPGAs are commonly used in industry and academia due to their area, speed, and power benefits over their homogeneous counterparts. These FPGAs contain a mixture of logic blocks and hard blocks where hard blocks are arranged in fixed columns as they offer an easy and compact...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2011-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2011/121404 |
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| _version_ | 1832550909624713216 |
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| author | Umer Farooq Husain Parvez Habib Mehrez Zied Marrakchi |
| author_facet | Umer Farooq Husain Parvez Habib Mehrez Zied Marrakchi |
| author_sort | Umer Farooq |
| collection | DOAJ |
| description | Mesh-based heterogeneous FPGAs are commonly
used in industry and academia due to their area, speed, and power benefits over their homogeneous counterparts. These FPGAs contain a mixture of logic blocks and hard blocks where hard blocks
are arranged in fixed columns as they offer an easy and compact layout. However, the placement of hard-blocks in
fixed columns can potentially lead to underutilization of logic and routing resources and this problem is further aggravated with increase in the types of hard-blocks. This work explores and compares different floor-planning techniques of mesh-based FPGA to determine their effect on the area, performance, and power of the architecture. A tree-based architecture is also presented; unlike mesh-based architecture, the floor-planning of heterogeneous tree-based architecture does not affect its routing requirements due to its hierarchical structure. Both
mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results. |
| format | Article |
| id | doaj-art-69589e6d243e49109421707a1f574d98 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2011-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-69589e6d243e49109421707a1f574d982025-02-03T06:05:23ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092011-01-01201110.1155/2011/121404121404Exploration of Heterogeneous FPGA ArchitecturesUmer Farooq0Husain Parvez1Habib Mehrez2Zied Marrakchi3LIP6, UPMC, 75005 Paris, FranceLIP6, UPMC, 75005 Paris, FranceLIP6, UPMC, 75005 Paris, FranceFLEXRAS Technologies, 93521 Saint-Denis Cedex, FranceMesh-based heterogeneous FPGAs are commonly used in industry and academia due to their area, speed, and power benefits over their homogeneous counterparts. These FPGAs contain a mixture of logic blocks and hard blocks where hard blocks are arranged in fixed columns as they offer an easy and compact layout. However, the placement of hard-blocks in fixed columns can potentially lead to underutilization of logic and routing resources and this problem is further aggravated with increase in the types of hard-blocks. This work explores and compares different floor-planning techniques of mesh-based FPGA to determine their effect on the area, performance, and power of the architecture. A tree-based architecture is also presented; unlike mesh-based architecture, the floor-planning of heterogeneous tree-based architecture does not affect its routing requirements due to its hierarchical structure. Both mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.http://dx.doi.org/10.1155/2011/121404 |
| spellingShingle | Umer Farooq Husain Parvez Habib Mehrez Zied Marrakchi Exploration of Heterogeneous FPGA Architectures International Journal of Reconfigurable Computing |
| title | Exploration of Heterogeneous FPGA Architectures |
| title_full | Exploration of Heterogeneous FPGA Architectures |
| title_fullStr | Exploration of Heterogeneous FPGA Architectures |
| title_full_unstemmed | Exploration of Heterogeneous FPGA Architectures |
| title_short | Exploration of Heterogeneous FPGA Architectures |
| title_sort | exploration of heterogeneous fpga architectures |
| url | http://dx.doi.org/10.1155/2011/121404 |
| work_keys_str_mv | AT umerfarooq explorationofheterogeneousfpgaarchitectures AT husainparvez explorationofheterogeneousfpgaarchitectures AT habibmehrez explorationofheterogeneousfpgaarchitectures AT ziedmarrakchi explorationofheterogeneousfpgaarchitectures |