The Big Chip: Challenge, model and architecture
As Moore’s Law comes to an end, the implementation of high-performance chips through transistor scaling has become increasingly challenging. To improve performance, increasing the chip area to integrate more transistors has become an essential approach. However, due to restrictions such as the maxim...
Saved in:
| Main Authors: | Yinhe Han, Haobo Xu, Meixuan Lu, Haoran Wang, Junpei Huang, Ying Wang, Yujie Wang, Feng Min, Qi Liu, Ming Liu, Ninghui Sun |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
KeAi Communications Co. Ltd.
2024-11-01
|
| Series: | Fundamental Research |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2667325823003709 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Development of Artificial Intelligence Chips in China
by: Jiaqing Wu, et al.
Published: (2025-02-01) -
Hardware/Software Implementation of a Chip-to-Chip Communication Protocol Based on SPDM
by: Kais Belwafi, et al.
Published: (2024-01-01) -
Standard: human liver-on-a-chip
by: Haitao Liu, et al.
Published: (2025-03-01) -
Organ-on-a-chip Technology in Urology
by: A. G. Vardikian, et al.
Published: (2023-12-01) -
Networking strategy for wireless chip area network on PCB
by: Xuehua LI, et al.
Published: (2016-02-01)