Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth
A 10-b self-timed SAR A/D converter is designed in 28-nm FDSOI CMOS to convert at 500 MS/s. It maintains this effective number of bits across an input bandwidth of 2 GHz, because it will be used as one of eight identical converters in a time-interleaved system to reach a conversion rate of 4 GS/s. T...
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| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10695771/ |
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| author | Tetsuya Iizuka Ritaro Takenaka Hao Xu Asad A. Abidi |
| author_facet | Tetsuya Iizuka Ritaro Takenaka Hao Xu Asad A. Abidi |
| author_sort | Tetsuya Iizuka |
| collection | DOAJ |
| description | A 10-b self-timed SAR A/D converter is designed in 28-nm FDSOI CMOS to convert at 500 MS/s. It maintains this effective number of bits across an input bandwidth of 2 GHz, because it will be used as one of eight identical converters in a time-interleaved system to reach a conversion rate of 4 GS/s. This circuit is based almost entirely on formal expressions for every building block circuit. This approach led to a strikingly short development time where every design choice was defensibly optimum and the prototype chip yielded near-textbook performance from the first silicon. The figure of merit is at the state of the art. |
| format | Article |
| id | doaj-art-662213dd6b8545b7a3b704347a1e58b1 |
| institution | Kabale University |
| issn | 2644-1349 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj-art-662213dd6b8545b7a3b704347a1e58b12025-01-25T00:03:14ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492024-01-01414716210.1109/OJSSCS.2024.346910910695771Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution BandwidthTetsuya Iizuka0https://orcid.org/0000-0002-1512-4714Ritaro Takenaka1Hao Xu2https://orcid.org/0000-0002-0044-1231Asad A. Abidi3https://orcid.org/0000-0002-7064-0738Systems Design Laboratory, School of Engineering, The University of Tokyo, Tokyo, JapanDepartment of Electrical Engineering and Information Systems, School of Engineering, The University of Tokyo, Tokyo, JapanState Key Laboratory of Integrated Chip and Systems, School of Microelectronics, Fudan University, Shanghai, ChinaElectrical and Computer Engineering Department, University of California, Los Angeles, CA, USAA 10-b self-timed SAR A/D converter is designed in 28-nm FDSOI CMOS to convert at 500 MS/s. It maintains this effective number of bits across an input bandwidth of 2 GHz, because it will be used as one of eight identical converters in a time-interleaved system to reach a conversion rate of 4 GS/s. This circuit is based almost entirely on formal expressions for every building block circuit. This approach led to a strikingly short development time where every design choice was defensibly optimum and the prototype chip yielded near-textbook performance from the first silicon. The figure of merit is at the state of the art.https://ieeexplore.ieee.org/document/10695771/Analog-to-digital converterharmonic distortionjitterregenerative comparatorsample and hold (S/H)systematic design |
| spellingShingle | Tetsuya Iizuka Ritaro Takenaka Hao Xu Asad A. Abidi Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth IEEE Open Journal of the Solid-State Circuits Society Analog-to-digital converter harmonic distortion jitter regenerative comparator sample and hold (S/H) systematic design |
| title | Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth |
| title_full | Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth |
| title_fullStr | Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth |
| title_full_unstemmed | Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth |
| title_short | Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth |
| title_sort | systematic equation based design of a 10 bit 500 ms s single channel sar a d converter with 2 ghz resolution bandwidth |
| topic | Analog-to-digital converter harmonic distortion jitter regenerative comparator sample and hold (S/H) systematic design |
| url | https://ieeexplore.ieee.org/document/10695771/ |
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