Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications
The multipliers are essential components in real-time applications. Although approximation arithmetic affects the output accuracy in multipliers, it offers a realistic avenue for constructing power-, area--, and speed-efficient digital circuits. The approximation computing technique is commonly used...
Saved in:
Main Authors: | Venkata Sudhakar Chowdam, Suresh Babu Potladurty, Prasad Reddy karipireddy |
---|---|
Format: | Article |
Language: | English |
Published: |
Elsevier
2025-04-01
|
Series: | Memories - Materials, Devices, Circuits and Systems |
Subjects: | |
Online Access: | http://www.sciencedirect.com/science/article/pii/S2773064625000039 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier
by: Laimin Du, et al.
Published: (2024-01-01) -
Analysis and Verilog-A Modeling of Floating-Gate Transistors
by: Sayma Nowshin Chowdhury, et al.
Published: (2025-01-01) -
Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit
by: Katyayani Chauhan, et al.
Published: (2025-03-01) -
V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation
by: Chao Wang, et al.
Published: (2024-01-01) -
Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication
by: Geetam Singh Tomar, et al.
Published: (2021-08-01)