Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications
The multipliers are essential components in real-time applications. Although approximation arithmetic affects the output accuracy in multipliers, it offers a realistic avenue for constructing power-, area--, and speed-efficient digital circuits. The approximation computing technique is commonly used...
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Elsevier
2025-04-01
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| Series: | Memories - Materials, Devices, Circuits and Systems |
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| Online Access: | http://www.sciencedirect.com/science/article/pii/S2773064625000039 |
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| author | Venkata Sudhakar Chowdam Suresh Babu Potladurty Prasad Reddy karipireddy |
| author_facet | Venkata Sudhakar Chowdam Suresh Babu Potladurty Prasad Reddy karipireddy |
| author_sort | Venkata Sudhakar Chowdam |
| collection | DOAJ |
| description | The multipliers are essential components in real-time applications. Although approximation arithmetic affects the output accuracy in multipliers, it offers a realistic avenue for constructing power-, area--, and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this study, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HAs) and full adders (A-FAs), which are strategically placed to add partial products at the most significant bit (MSB) positions, and OR gates are used to add partial products at the lower significant bit (LSB). In addition, this research article demonstrates unsigned and signed multipliers using the Ripple Carry Adder (RCA), Carry Save Adder (CSA), Conditional Sum Adder (COSA), Carry Select Adder (CSLA), and Clock Gating Technique. The proposed multipliers are implemented in Verilog HDL and simulated on the Xilinx VIVADO 2021.2 design tool, with the target platform being the Artix-7 AC701 FPGA. The results found that the power dissipation change is 13%, the delay change is 4.7%, and the area change is 15% for the 16-bit unsigned approximate multiplier. For the 16-bit signed approximate multiplier, the power change is 18.81%, the delay change is 3.57%, and the area change is 14.29% using inexact and exact adders and the clock gating technique with CSA as the final partial product summer. Clock-gating 16-bit multiplier RED decreases when compared to approximate adder usage alone in the multiplier. The proposed multipliers are useful in error-tolerant applications such as digital signal processing, image fusion, image blending, smoothing, and sharpening to produce high-quality images at high speed and with low power consumption. |
| format | Article |
| id | doaj-art-554e0fe67b504f35849d8291a01a184c |
| institution | Kabale University |
| issn | 2773-0646 |
| language | English |
| publishDate | 2025-04-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Memories - Materials, Devices, Circuits and Systems |
| spelling | doaj-art-554e0fe67b504f35849d8291a01a184c2025-01-28T04:15:00ZengElsevierMemories - Materials, Devices, Circuits and Systems2773-06462025-04-019100123Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applicationsVenkata Sudhakar Chowdam0Suresh Babu Potladurty1Prasad Reddy karipireddy2Department of Electronics and Communication Engineering, School of Engineering, Mohan Babu University (Erstwhile Sree Vidyanikethan Engineering College), Tirupati, 517102, India; Corresponding author.Department of Electronics and Communication Engineering, Sri Venkateswara College of Engineering, Tirupati, 517507, IndiaFunctional Safety Expert, Keilasatama 5, ESPOO, 02150, FinlandThe multipliers are essential components in real-time applications. Although approximation arithmetic affects the output accuracy in multipliers, it offers a realistic avenue for constructing power-, area--, and speed-efficient digital circuits. The approximation computing technique is commonly used in error-tolerant applications such as signal, image, and video processing. In this study, approximate multipliers (AMs) are designed using both conventional and approximate half adders (A-HAs) and full adders (A-FAs), which are strategically placed to add partial products at the most significant bit (MSB) positions, and OR gates are used to add partial products at the lower significant bit (LSB). In addition, this research article demonstrates unsigned and signed multipliers using the Ripple Carry Adder (RCA), Carry Save Adder (CSA), Conditional Sum Adder (COSA), Carry Select Adder (CSLA), and Clock Gating Technique. The proposed multipliers are implemented in Verilog HDL and simulated on the Xilinx VIVADO 2021.2 design tool, with the target platform being the Artix-7 AC701 FPGA. The results found that the power dissipation change is 13%, the delay change is 4.7%, and the area change is 15% for the 16-bit unsigned approximate multiplier. For the 16-bit signed approximate multiplier, the power change is 18.81%, the delay change is 3.57%, and the area change is 14.29% using inexact and exact adders and the clock gating technique with CSA as the final partial product summer. Clock-gating 16-bit multiplier RED decreases when compared to approximate adder usage alone in the multiplier. The proposed multipliers are useful in error-tolerant applications such as digital signal processing, image fusion, image blending, smoothing, and sharpening to produce high-quality images at high speed and with low power consumption.http://www.sciencedirect.com/science/article/pii/S2773064625000039Approximate computingApproximate addersClock-gating multiplierVerilog HDLFPGA implementationPower efficiency |
| spellingShingle | Venkata Sudhakar Chowdam Suresh Babu Potladurty Prasad Reddy karipireddy Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications Memories - Materials, Devices, Circuits and Systems Approximate computing Approximate adders Clock-gating multiplier Verilog HDL FPGA implementation Power efficiency |
| title | Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications |
| title_full | Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications |
| title_fullStr | Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications |
| title_full_unstemmed | Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications |
| title_short | Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications |
| title_sort | design and evaluation of clock gating based approximate multiplier for error tolerant applications |
| topic | Approximate computing Approximate adders Clock-gating multiplier Verilog HDL FPGA implementation Power efficiency |
| url | http://www.sciencedirect.com/science/article/pii/S2773064625000039 |
| work_keys_str_mv | AT venkatasudhakarchowdam designandevaluationofclockgatingbasedapproximatemultiplierforerrortolerantapplications AT sureshbabupotladurty designandevaluationofclockgatingbasedapproximatemultiplierforerrortolerantapplications AT prasadreddykaripireddy designandevaluationofclockgatingbasedapproximatemultiplierforerrortolerantapplications |