Insights Into Architectural Spurs in High-Performance Fractional-<italic>N</italic> Frequency Synthesizers
A fractional-N frequency synthesizer inherently exhibits spurs by virtue of the fact that its output frequency is not an integer multiple of its reference frequency. Until recently, it seemed that fractional spurs were understood and under control. However, as higher performance is demanded of frequ...
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10648812/ |
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| author | Michael Peter Kennedy Xu Lu Xu Wang |
| author_facet | Michael Peter Kennedy Xu Lu Xu Wang |
| author_sort | Michael Peter Kennedy |
| collection | DOAJ |
| description | A fractional-N frequency synthesizer inherently exhibits spurs by virtue of the fact that its output frequency is not an integer multiple of its reference frequency. Until recently, it seemed that fractional spurs were understood and under control. However, as higher performance is demanded of frequency synthesizers, new spur production mechanisms and phenomena have been reported. This has led to intense research efforts to understand what is causing these problems and to develop methods to mitigate them. This article reviews what is known, highlights some recent advances in understanding and mitigation techniques, and flags new challenges in digital-intensive architectures. It focuses exclusively on spur mechanisms that are inherent in the architecture (rather than due to coupling or packaging issues) and therefore are amenable to architectural solutions. |
| format | Article |
| id | doaj-art-4e8915cf539a4a35884eb0db9c709b45 |
| institution | Kabale University |
| issn | 2644-1349 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj-art-4e8915cf539a4a35884eb0db9c709b452025-01-25T00:03:19ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492024-01-01423825110.1109/OJSSCS.2024.345041010648812Insights Into Architectural Spurs in High-Performance Fractional-<italic>N</italic> Frequency SynthesizersMichael Peter Kennedy0https://orcid.org/0000-0003-3242-1056Xu Lu1https://orcid.org/0009-0007-6287-6832Xu Wang2https://orcid.org/0000-0002-4849-7306School of Electrical and Electronic Engineering, University College Dublin, Dublin 4, IrelandSchool of Electrical and Electronic Engineering, University College Dublin, Dublin 4, IrelandSchool of Electrical and Electronic Engineering, University College Dublin, Dublin 4, IrelandA fractional-N frequency synthesizer inherently exhibits spurs by virtue of the fact that its output frequency is not an integer multiple of its reference frequency. Until recently, it seemed that fractional spurs were understood and under control. However, as higher performance is demanded of frequency synthesizers, new spur production mechanisms and phenomena have been reported. This has led to intense research efforts to understand what is causing these problems and to develop methods to mitigate them. This article reviews what is known, highlights some recent advances in understanding and mitigation techniques, and flags new challenges in digital-intensive architectures. It focuses exclusively on spur mechanisms that are inherent in the architecture (rather than due to coupling or packaging issues) and therefore are amenable to architectural solutions.https://ieeexplore.ieee.org/document/10648812/Digital delta-sigma modulator (DDSM)fractional-N phase-locked loop (PLL)frequency synthesizernonlinearity |
| spellingShingle | Michael Peter Kennedy Xu Lu Xu Wang Insights Into Architectural Spurs in High-Performance Fractional-<italic>N</italic> Frequency Synthesizers IEEE Open Journal of the Solid-State Circuits Society Digital delta-sigma modulator (DDSM) fractional-N phase-locked loop (PLL) frequency synthesizer nonlinearity |
| title | Insights Into Architectural Spurs in High-Performance Fractional-<italic>N</italic> Frequency Synthesizers |
| title_full | Insights Into Architectural Spurs in High-Performance Fractional-<italic>N</italic> Frequency Synthesizers |
| title_fullStr | Insights Into Architectural Spurs in High-Performance Fractional-<italic>N</italic> Frequency Synthesizers |
| title_full_unstemmed | Insights Into Architectural Spurs in High-Performance Fractional-<italic>N</italic> Frequency Synthesizers |
| title_short | Insights Into Architectural Spurs in High-Performance Fractional-<italic>N</italic> Frequency Synthesizers |
| title_sort | insights into architectural spurs in high performance fractional italic n italic frequency synthesizers |
| topic | Digital delta-sigma modulator (DDSM) fractional-N phase-locked loop (PLL) frequency synthesizer nonlinearity |
| url | https://ieeexplore.ieee.org/document/10648812/ |
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