Don’t Cache, Speculate!: Speculative Address Translation for Flash-Based Storage Systems
Address translation using a logical-to-physical (L2P) mapping table is essential for the NAND Flash-based SSDs. Unfortunately, the L2P mapping table size increases as SSD capacity increases. The mapping table is basically stored in the NAND flash, and a small number of the table entries are cached i...
Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
|
| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10843687/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832576752701931520 |
|---|---|
| author | Hyungjin Kim Seongwook Kim Junhyeok Park Gwangeun Byeon Seokin Hong |
| author_facet | Hyungjin Kim Seongwook Kim Junhyeok Park Gwangeun Byeon Seokin Hong |
| author_sort | Hyungjin Kim |
| collection | DOAJ |
| description | Address translation using a logical-to-physical (L2P) mapping table is essential for the NAND Flash-based SSDs. Unfortunately, the L2P mapping table size increases as SSD capacity increases. The mapping table is basically stored in the NAND flash, and a small number of the table entries are cached in the DRAM, leading to performance degradation due to the overhead of loading the mapping table entries from the slow NAND flash. The performance overhead of the address translation is more severe in low-cost flash-based storage systems (e.g., DRAM-less SSD) because they do not employ the DRAM for caching the mapping table, and thus, every I/O request involves an additional read request to the flash to load an address mapping information. To tackle the address translation overhead in the SSDs, this paper proposes ASTRO framework that speculatively translates the logical addresses to physical ones by maintaining the contiguity in the address mappings as much as possible. ASTRO consists of three novel mechanisms: 1) Lazy Page Ordering (LPO) to rearrange the pages to maintain the contiguity in the address mappings for each region, 2) Speculative Read (SpecREAD) to convert logical addresses to physical addresses speculatively, and 3) Contiguity Checking (ContCHECK) to monitor the updates in the rearranged regions. These three mechanisms are implemented in the FTL software, and some functions are accelerated by adding simple hardware to the SSD controller. Experimental results demonstrate that ASTRO enhances SSD performance by an average of 80% and 34% for synthetic random read workloads and real-world workloads, respectively, while minimally impacting the write amplification factor. |
| format | Article |
| id | doaj-art-493c9c0d890f441f974f8e24dcf356da |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-493c9c0d890f441f974f8e24dcf356da2025-01-31T00:00:53ZengIEEEIEEE Access2169-35362025-01-0113185241853410.1109/ACCESS.2025.353077610843687Don’t Cache, Speculate!: Speculative Address Translation for Flash-Based Storage SystemsHyungjin Kim0https://orcid.org/0009-0009-1504-1247Seongwook Kim1Junhyeok Park2https://orcid.org/0009-0003-3802-7524Gwangeun Byeon3Seokin Hong4https://orcid.org/0000-0001-7842-125XDepartment of Semiconductor and Display Engineering, Sungkyunkwan University, Suwon, Republic of KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Republic of KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Republic of KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Republic of KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Republic of KoreaAddress translation using a logical-to-physical (L2P) mapping table is essential for the NAND Flash-based SSDs. Unfortunately, the L2P mapping table size increases as SSD capacity increases. The mapping table is basically stored in the NAND flash, and a small number of the table entries are cached in the DRAM, leading to performance degradation due to the overhead of loading the mapping table entries from the slow NAND flash. The performance overhead of the address translation is more severe in low-cost flash-based storage systems (e.g., DRAM-less SSD) because they do not employ the DRAM for caching the mapping table, and thus, every I/O request involves an additional read request to the flash to load an address mapping information. To tackle the address translation overhead in the SSDs, this paper proposes ASTRO framework that speculatively translates the logical addresses to physical ones by maintaining the contiguity in the address mappings as much as possible. ASTRO consists of three novel mechanisms: 1) Lazy Page Ordering (LPO) to rearrange the pages to maintain the contiguity in the address mappings for each region, 2) Speculative Read (SpecREAD) to convert logical addresses to physical addresses speculatively, and 3) Contiguity Checking (ContCHECK) to monitor the updates in the rearranged regions. These three mechanisms are implemented in the FTL software, and some functions are accelerated by adding simple hardware to the SSD controller. Experimental results demonstrate that ASTRO enhances SSD performance by an average of 80% and 34% for synthetic random read workloads and real-world workloads, respectively, while minimally impacting the write amplification factor.https://ieeexplore.ieee.org/document/10843687/Flash translation layeraddress translationstorage system |
| spellingShingle | Hyungjin Kim Seongwook Kim Junhyeok Park Gwangeun Byeon Seokin Hong Don’t Cache, Speculate!: Speculative Address Translation for Flash-Based Storage Systems IEEE Access Flash translation layer address translation storage system |
| title | Don’t Cache, Speculate!: Speculative Address Translation for Flash-Based Storage Systems |
| title_full | Don’t Cache, Speculate!: Speculative Address Translation for Flash-Based Storage Systems |
| title_fullStr | Don’t Cache, Speculate!: Speculative Address Translation for Flash-Based Storage Systems |
| title_full_unstemmed | Don’t Cache, Speculate!: Speculative Address Translation for Flash-Based Storage Systems |
| title_short | Don’t Cache, Speculate!: Speculative Address Translation for Flash-Based Storage Systems |
| title_sort | don x2019 t cache speculate speculative address translation for flash based storage systems |
| topic | Flash translation layer address translation storage system |
| url | https://ieeexplore.ieee.org/document/10843687/ |
| work_keys_str_mv | AT hyungjinkim donx2019tcachespeculatespeculativeaddresstranslationforflashbasedstoragesystems AT seongwookkim donx2019tcachespeculatespeculativeaddresstranslationforflashbasedstoragesystems AT junhyeokpark donx2019tcachespeculatespeculativeaddresstranslationforflashbasedstoragesystems AT gwangeunbyeon donx2019tcachespeculatespeculativeaddresstranslationforflashbasedstoragesystems AT seokinhong donx2019tcachespeculatespeculativeaddresstranslationforflashbasedstoragesystems |