AC_ICAP: A Flexible High Speed ICAP Controller
The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs). We developed a new high speed ICAP controller, named AC_ICAP, completely implemented in hardware. In addition to s...
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| Format: | Article |
| Language: | English |
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Wiley
2015-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2015/314358 |
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| author | Luis Andres Cardona Carles Ferrer |
| author_facet | Luis Andres Cardona Carles Ferrer |
| author_sort | Luis Andres Cardona |
| collection | DOAJ |
| description | The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs). We developed a new high speed ICAP controller, named AC_ICAP, completely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and frames, AC_ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last characteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this hardware-based solution to provide IP cores accessible from the MicroBlaze processor. To this end, the controller was extended and three versions were implemented to evaluate its performance when connected to Peripheral Local Bus (PLB), Fast Simplex Link (FSL), and AXI interfaces of the processor. In consequence, the controller can exploit the flexibility that the processor offers but taking advantage of the hardware speed-up. It was implemented in both Virtex-5 and Kintex7 FPGAs. Results of reconfiguration time showed that run-time reconfiguration of single LUTs in Virtex-5 devices was performed in less than 5 μs which implies a speed-up of more than 380x compared to the Xilinx XPS_HWICAP controller. |
| format | Article |
| id | doaj-art-492090921ea1402dbbded75b47dae027 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2015-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-492090921ea1402dbbded75b47dae0272025-02-03T06:44:30ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092015-01-01201510.1155/2015/314358314358AC_ICAP: A Flexible High Speed ICAP ControllerLuis Andres Cardona0Carles Ferrer1Departament Microelectrònica i Sistemes Electrònics, Universitat Autònoma de Barcelona (IEEC-UAB), Bellaterra, 08193 Barcelona, SpainDepartament Microelectrònica i Sistemes Electrònics, Universitat Autònoma de Barcelona (IEEC-UAB), Bellaterra, 08193 Barcelona, SpainThe Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs). We developed a new high speed ICAP controller, named AC_ICAP, completely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and frames, AC_ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last characteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this hardware-based solution to provide IP cores accessible from the MicroBlaze processor. To this end, the controller was extended and three versions were implemented to evaluate its performance when connected to Peripheral Local Bus (PLB), Fast Simplex Link (FSL), and AXI interfaces of the processor. In consequence, the controller can exploit the flexibility that the processor offers but taking advantage of the hardware speed-up. It was implemented in both Virtex-5 and Kintex7 FPGAs. Results of reconfiguration time showed that run-time reconfiguration of single LUTs in Virtex-5 devices was performed in less than 5 μs which implies a speed-up of more than 380x compared to the Xilinx XPS_HWICAP controller.http://dx.doi.org/10.1155/2015/314358 |
| spellingShingle | Luis Andres Cardona Carles Ferrer AC_ICAP: A Flexible High Speed ICAP Controller International Journal of Reconfigurable Computing |
| title | AC_ICAP: A Flexible High Speed ICAP Controller |
| title_full | AC_ICAP: A Flexible High Speed ICAP Controller |
| title_fullStr | AC_ICAP: A Flexible High Speed ICAP Controller |
| title_full_unstemmed | AC_ICAP: A Flexible High Speed ICAP Controller |
| title_short | AC_ICAP: A Flexible High Speed ICAP Controller |
| title_sort | ac icap a flexible high speed icap controller |
| url | http://dx.doi.org/10.1155/2015/314358 |
| work_keys_str_mv | AT luisandrescardona acicapaflexiblehighspeedicapcontroller AT carlesferrer acicapaflexiblehighspeedicapcontroller |