Compiler Optimization of Wide Memory Access for Aarch64 - Viacheslav Chernonog; Emin Gadzhiev; Andrey Dobrov (Современные информационные технологии и IT-образование)
The popularity of ARM-based processors in HPC and cloud computing is gradually increasing and the development of compilers and code optimizations is important to achieve better use of hardware resources. It is well known that memory operations have a significant impact on performance. There are load and store instructions in Aarch64 ISA (LDP, LDPSW, STP) that can be used to access a wide memory range. Compilers use these instructions in architecture-dependent peephole optimizations to replace sequence of load/store instructions. In this paper, the pros and cons of such optimization are considered, some cases are taken into account and analyzed by simulation to identify a potential performance improvement opportunity. Next, compiler optimization is proposed to find and replace with two memory loads those LDP (LDPSW) instructions part of the data of which can be obtained by the store-to-load forwarding hardware mechanism. The performance evaluation shows that the proposed optimization improves performance for applications RapidJSON (by 5% on single-core run and 3% on all-core run), tpcc (16% on single-core run) and tpch (2% on all-core run).