Parametric Yield-Driven Resource Binding in High-Level Synthesis with Multi-Vth/Vdd Library and Device Sizing
The ever-increasing chip power dissipation in SoCs has imposed great challenges on today’s circuit design. It has been shown that multiple threshold and supply voltages assignment (multi-Vth/Vdd) is an effective way to reduce power dissipation. However, most of the prior multi-Vth/Vdd optimizations...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2012-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2012/105250 |
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| Summary: | The ever-increasing chip power dissipation in SoCs
has imposed great challenges on today’s circuit design. It has been
shown that multiple threshold and supply voltages assignment
(multi-Vth/Vdd) is an effective way to reduce power dissipation.
However, most of the prior multi-Vth/Vdd optimizations are
performed under deterministic conditions. With the increasing
process variability that has significant impact on both the power
dissipation and performance of circuit designs, it is necessary to
employ statistical approaches in analysis and optimizations for
low power. This paper studies the impact of process variations
on the multi-Vth/Vdd technique at the behavioral synthesis level. A multi-Vth/Vdd resource library is characterized for delay and
power variations at different voltage combinations. Meanwhile,
device sizing is performed on the resources in the library to
mitigate the impact of variation, and to enlarge the design
space for better quality of the design choice. A parametric yield-driven
resource binding algorithm is then proposed, which uses
the characterized power and delay distributions and efficiently
maximizes power yield under a timing yield constraint. During
the resource binding process, voltage level converters are inserted
between resources when required. Experimental results show that
significant power reduction can be achieved with the proposed
variation-aware framework, compared with traditional worstcase
based deterministic approaches. |
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| ISSN: | 2090-0147 2090-0155 |