A Four-Phase Digital Buck Converter With MDLL-Based Adaptive Switching Frequency Compensation - Muhammad Abrar Akram; Ibrar Ali Wahla; Kyung-Sung Kim; In-Chul Hwang (IEEE Access)
This paper presents a digitally-controlled 4-phase DC-DC buck converter that achieves ripple-less, fast responsive voltage conversion and regulation with high power efficiency, along with effective load and line regulation. Digital buck converters typically exhibit lower power efficiency due to conduction losses, which can occur when the switching pulse duty cycle decreases. To address this, the proposed buck converter employs a multiplying delay-locked loop (MDLL) based adaptive-switching frequency compensation (ASFC) technique. The proposed ASFC significantly reduces conduction losses by adaptively adjusting the switching frequency. Additionally, it lowers the switching frequency when the switching duty cycle decreases reducing switching losses and thereby enhancing power efficiency. Furthermore, the implementation of a 4-phase design in the proposed digital buck converter helps to reduce output voltage ripples, improve transient response time, and increase the load current range. The proposed buck converter was designed and fabricated in a 65-nm CMOS process, occupying an overall chip area of $2~mm^{2}$ . Measurement results demonstrate that the inclusion of the MDLL-based ASFC improves the overall power efficiency of the buck converter by more than $5~%$ , achieving a peak power efficiency of $87.6~%$ . Furthermore, the proposed buck converter recovers from an undershoot of 36 mV within $2.8~μ $ s for a load current step of 290 mA.