DC‐offset elimination method for grid synchronisation
For three‐phase power system, the synchronous reference frame (SRF) phase‐locked loop (PLL) is probably the most widely used synchronisation technique under ideal grid condition. However, the presence of dc‐offset causes fundamental frequency oscillations errors in estimated phase. To deal with this...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2017-03-01
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| Series: | Electronics Letters |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/el.2016.4570 |
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| Summary: | For three‐phase power system, the synchronous reference frame (SRF) phase‐locked loop (PLL) is probably the most widely used synchronisation technique under ideal grid condition. However, the presence of dc‐offset causes fundamental frequency oscillations errors in estimated phase. To deal with this problem, delay signal cancellation (DSC) operator is utilised in SRF‐PLL in recent published literature at the cost of slowing down the dynamic behaviour. The aim is to propose a rapid dc‐offset rejection method in three‐phase PLL for grid synchronisation. With the employment of modified DSC operator, the dynamic performance of the conventional DSC‐based PLL is improved. The effectiveness of the proposed method is confirmed through simulation results. |
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| ISSN: | 0013-5194 1350-911X |