Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture
Abstract SM3 hash algorithm developed by the Chinese Government is used in various fields of information security, and it is being widely used in commercial security products. However, the performance of implementation on the software architecture is not sufficient for high‐speed applications. This...
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| Format: | Article |
| Language: | English |
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Wiley
2021-11-01
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| Series: | IET Computers & Digital Techniques |
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| Online Access: | https://doi.org/10.1049/cdt2.12034 |
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| author | Xiaoying Huang Zhichuan Guo Mangu Song Xuewen Zeng |
| author_facet | Xiaoying Huang Zhichuan Guo Mangu Song Xuewen Zeng |
| author_sort | Xiaoying Huang |
| collection | DOAJ |
| description | Abstract SM3 hash algorithm developed by the Chinese Government is used in various fields of information security, and it is being widely used in commercial security products. However, the performance of implementation on the software architecture is not sufficient for high‐speed applications. This study proposes a CPU‐FPGA co‐designed architecture which offloads the SM3 function on field‐programmable gate array so that high throughput can be achieved. The architecture can execute the SM3 hash algorithm with 16 concurrent streams or more, which means that multiple data streams can be processed in parallel. This design is implemented on the Xilinx XCKU115‐flva1517‐2‐e device and Dell commercial server, and the throughput of this design can reach up to 35.5 Gbps when 16 individual SM3 modules are processed in parallel. The proposed architecture results in an excellent performance in the CPU‐FPGA‐coupled environment. |
| format | Article |
| id | doaj-art-3ecde64b87f84fba8e4774552fb6de21 |
| institution | Kabale University |
| issn | 1751-8601 1751-861X |
| language | English |
| publishDate | 2021-11-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Computers & Digital Techniques |
| spelling | doaj-art-3ecde64b87f84fba8e4774552fb6de212025-02-03T01:29:24ZengWileyIET Computers & Digital Techniques1751-86011751-861X2021-11-0115642743610.1049/cdt2.12034Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architectureXiaoying Huang0Zhichuan Guo1Mangu Song2Xuewen Zeng3National Network New Media Engineering Research Center Institute of Acoustics, Chinese Academy of Sciences Beijing ChinaNational Network New Media Engineering Research Center Institute of Acoustics, Chinese Academy of Sciences Beijing ChinaNational Network New Media Engineering Research Center Institute of Acoustics, Chinese Academy of Sciences Beijing ChinaNational Network New Media Engineering Research Center Institute of Acoustics, Chinese Academy of Sciences Beijing ChinaAbstract SM3 hash algorithm developed by the Chinese Government is used in various fields of information security, and it is being widely used in commercial security products. However, the performance of implementation on the software architecture is not sufficient for high‐speed applications. This study proposes a CPU‐FPGA co‐designed architecture which offloads the SM3 function on field‐programmable gate array so that high throughput can be achieved. The architecture can execute the SM3 hash algorithm with 16 concurrent streams or more, which means that multiple data streams can be processed in parallel. This design is implemented on the Xilinx XCKU115‐flva1517‐2‐e device and Dell commercial server, and the throughput of this design can reach up to 35.5 Gbps when 16 individual SM3 modules are processed in parallel. The proposed architecture results in an excellent performance in the CPU‐FPGA‐coupled environment.https://doi.org/10.1049/cdt2.12034field programmable gate arrayscryptographysoftware architectureparallel architecturesmicroprocessor chips |
| spellingShingle | Xiaoying Huang Zhichuan Guo Mangu Song Xuewen Zeng Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture IET Computers & Digital Techniques field programmable gate arrays cryptography software architecture parallel architectures microprocessor chips |
| title | Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture |
| title_full | Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture |
| title_fullStr | Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture |
| title_full_unstemmed | Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture |
| title_short | Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture |
| title_sort | accelerating the sm3 hash algorithm with cpu fpga co designed architecture |
| topic | field programmable gate arrays cryptography software architecture parallel architectures microprocessor chips |
| url | https://doi.org/10.1049/cdt2.12034 |
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