Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit
This article proposed the use of an efficient ternary multiplexer as a building block in the implementation of ternary adders and multipliers. These designs aim to reduce the power consumption and minimize the transistor counts while maintaining low noise sensitivity. All ternary circuits use carbon...
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| Language: | English |
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Elsevier
2025-03-01
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| Series: | e-Prime: Advances in Electrical Engineering, Electronics and Energy |
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| Online Access: | http://www.sciencedirect.com/science/article/pii/S2772671125000191 |
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| author | Katyayani Chauhan Deepika Bansal |
| author_facet | Katyayani Chauhan Deepika Bansal |
| author_sort | Katyayani Chauhan |
| collection | DOAJ |
| description | This article proposed the use of an efficient ternary multiplexer as a building block in the implementation of ternary adders and multipliers. These designs aim to reduce the power consumption and minimize the transistor counts while maintaining low noise sensitivity. All ternary circuits use carbon nanotube field-effect transistor technology to achieve all levels due to the variable threshold property. The proposed ternary circuits have been evaluated and compared to state-of-the-art designs in the literature using the HSPICE simulator. The average power consumption of the proposed ternary multiplexer has improved up to 95 %. The average power of the proposed ternary half adder is improved by 99 % and the power-delay product of it is reduced up to 99 %. The proposed ternary multiplier and ternary half adder have reduced the transistor count by up to 60 % and 36 % respectively, in comparison to existing designs. The delay of the proposed ternary multiplier and ternary half adder has been reduced by up to 13 % and 93 %, respectively. |
| format | Article |
| id | doaj-art-3e8fabe9c2584f1c8bde67ae3956e891 |
| institution | Kabale University |
| issn | 2772-6711 |
| language | English |
| publishDate | 2025-03-01 |
| publisher | Elsevier |
| record_format | Article |
| series | e-Prime: Advances in Electrical Engineering, Electronics and Energy |
| spelling | doaj-art-3e8fabe9c2584f1c8bde67ae3956e8912025-01-31T05:12:47ZengElseviere-Prime: Advances in Electrical Engineering, Electronics and Energy2772-67112025-03-0111100912Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unitKatyayani Chauhan0Deepika Bansal1Department of Electronics & Communication Engineering, Manipal University Jaipur, Jaipur, Rajasthan, IndiaCorresponding author.; Department of Electronics & Communication Engineering, Manipal University Jaipur, Jaipur, Rajasthan, IndiaThis article proposed the use of an efficient ternary multiplexer as a building block in the implementation of ternary adders and multipliers. These designs aim to reduce the power consumption and minimize the transistor counts while maintaining low noise sensitivity. All ternary circuits use carbon nanotube field-effect transistor technology to achieve all levels due to the variable threshold property. The proposed ternary circuits have been evaluated and compared to state-of-the-art designs in the literature using the HSPICE simulator. The average power consumption of the proposed ternary multiplexer has improved up to 95 %. The average power of the proposed ternary half adder is improved by 99 % and the power-delay product of it is reduced up to 99 %. The proposed ternary multiplier and ternary half adder have reduced the transistor count by up to 60 % and 36 % respectively, in comparison to existing designs. The delay of the proposed ternary multiplier and ternary half adder has been reduced by up to 13 % and 93 %, respectively.http://www.sciencedirect.com/science/article/pii/S2772671125000191Ternary circuitTernary half adderTernary multiplexerTernary multiplierCNTFET |
| spellingShingle | Katyayani Chauhan Deepika Bansal Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit e-Prime: Advances in Electrical Engineering, Electronics and Energy Ternary circuit Ternary half adder Ternary multiplexer Ternary multiplier CNTFET |
| title | Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit |
| title_full | Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit |
| title_fullStr | Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit |
| title_full_unstemmed | Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit |
| title_short | Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit |
| title_sort | noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit |
| topic | Ternary circuit Ternary half adder Ternary multiplexer Ternary multiplier CNTFET |
| url | http://www.sciencedirect.com/science/article/pii/S2772671125000191 |
| work_keys_str_mv | AT katyayanichauhan noisetolerantandpoweroptimizedternarycombinationalcircuitsforarithmeticlogicunit AT deepikabansal noisetolerantandpoweroptimizedternarycombinationalcircuitsforarithmeticlogicunit |