APA (7th ed.) Citation

Chauhan, K., & Bansal, D. Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit. Elsevier.

Chicago Style (17th ed.) Citation

Chauhan, Katyayani, and Deepika Bansal. Noise Tolerant and Power Optimized Ternary Combinational Circuits for Arithmetic Logic Unit. Elsevier.

MLA (9th ed.) Citation

Chauhan, Katyayani, and Deepika Bansal. Noise Tolerant and Power Optimized Ternary Combinational Circuits for Arithmetic Logic Unit. Elsevier.

Warning: These citations may not always be 100% accurate.