Ibrahim, A. Low‐space bit‐serial systolic array architecture for interleaved multiplication over GF(2m). Wiley.
Chicago Style (17th ed.) CitationIbrahim, Atef. Low‐space Bit‐serial Systolic Array Architecture for Interleaved Multiplication over GF(2m). Wiley.
MLA (9th ed.) CitationIbrahim, Atef. Low‐space Bit‐serial Systolic Array Architecture for Interleaved Multiplication over GF(2m). Wiley.
Warning: These citations may not always be 100% accurate.