A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node
Combining with a static random-access memory (SRAM) and resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell is proposed in this study. With differential mode, a pair of 1T1R RRAM is added to 6T SRAM storage node. By optimizing the connection and layout scheme, the power c...
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| Format: | Article |
| Language: | English |
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Wiley
2023-01-01
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| Series: | Active and Passive Electronic Components |
| Online Access: | http://dx.doi.org/10.1155/2023/2364341 |
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| author | Jiayu Yin Wenli Liao Chengying Chen |
| author_facet | Jiayu Yin Wenli Liao Chengying Chen |
| author_sort | Jiayu Yin |
| collection | DOAJ |
| description | Combining with a static random-access memory (SRAM) and resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell is proposed in this study. With differential mode, a pair of 1T1R RRAM is added to 6T SRAM storage node. By optimizing the connection and layout scheme, the power consumption is reduced and the data stability is improved. The nvSRAM memory cell is realized with UMC CMOS 28 nm 1p9m process. When the power supply voltage is 0.9 V, the static noise/read/write margin is 0.35 V, 0.16 V, and 0.41 V, respectively. The data storage/restoration time is 0.21 ns and 0.18 ns, respectively, with an active area of 0.97 μm2. |
| format | Article |
| id | doaj-art-3b392060eddc42cba0093f2e350ec048 |
| institution | Kabale University |
| issn | 1563-5031 |
| language | English |
| publishDate | 2023-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Active and Passive Electronic Components |
| spelling | doaj-art-3b392060eddc42cba0093f2e350ec0482025-08-20T03:55:36ZengWileyActive and Passive Electronic Components1563-50312023-01-01202310.1155/2023/2364341A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology NodeJiayu Yin0Wenli Liao1Chengying Chen2School of Opto-Electronic and Communication EngineeringSchool of Opto-Electronic and Communication EngineeringSchool of Opto-Electronic and Communication EngineeringCombining with a static random-access memory (SRAM) and resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell is proposed in this study. With differential mode, a pair of 1T1R RRAM is added to 6T SRAM storage node. By optimizing the connection and layout scheme, the power consumption is reduced and the data stability is improved. The nvSRAM memory cell is realized with UMC CMOS 28 nm 1p9m process. When the power supply voltage is 0.9 V, the static noise/read/write margin is 0.35 V, 0.16 V, and 0.41 V, respectively. The data storage/restoration time is 0.21 ns and 0.18 ns, respectively, with an active area of 0.97 μm2.http://dx.doi.org/10.1155/2023/2364341 |
| spellingShingle | Jiayu Yin Wenli Liao Chengying Chen A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node Active and Passive Electronic Components |
| title | A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node |
| title_full | A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node |
| title_fullStr | A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node |
| title_full_unstemmed | A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node |
| title_short | A 0.9 V, 8T2R nvSRAM Memory Cell with High Density and Improved Storage/Restoration Time in 28 nm Technology Node |
| title_sort | 0 9 v 8t2r nvsram memory cell with high density and improved storage restoration time in 28 nm technology node |
| url | http://dx.doi.org/10.1155/2023/2364341 |
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