Design of High Performance Hybrid Type Digital-Feedback Low Drop-Out Regulator Using SSCG Technique
This paper proposes a high-performance Digital Feedback low-dropout voltage regulator (DF-LDO) for low power applications. In the DF-LDO regulator, digital feedback and applying spectrum spread clock generator (SSCG) technique are used to reduce output voltage ripples. In addition, it has triple ope...
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2021-01-01
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| Online Access: | https://ieeexplore.ieee.org/document/9347421/ |
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| author | Muhammad Asif Imran Ali Danial Khan Muhammad Riaz Ur Rehman Younggun Pu Sang-Sun Yoo Kang-Yoon Lee |
| author_facet | Muhammad Asif Imran Ali Danial Khan Muhammad Riaz Ur Rehman Younggun Pu Sang-Sun Yoo Kang-Yoon Lee |
| author_sort | Muhammad Asif |
| collection | DOAJ |
| description | This paper proposes a high-performance Digital Feedback low-dropout voltage regulator (DF-LDO) for low power applications. In the DF-LDO regulator, digital feedback and applying spectrum spread clock generator (SSCG) technique are used to reduce output voltage ripples. In addition, it has triple operation modes i.e. coarse, fine, and retention for high efficiency and transient enhancement. The proposed hybrid DF-LDO uses arrays of PMOS transistors in coarse and fine mode whereas in retention mode, only one comparator and NMOS are active and digital controller goes into the sleep mode. This results in the reduction of the power consumption and improves the output voltage ripples. In the retention mode, minimum number of blocks operate that reduces the current consumption as compared to coarse and fine modes. To further reduce the current consumption, the comparator with hysteresis is used. The proposed circuit is designed using CMOS 55 nm process. The input voltage range is from 0.8 ~ 1.5 V and the measured output voltage range is 0.756 ~ 1.456 V. The measured line regulation is 6 mV / V, and the regulation starts when the input voltage is 0.8 V. The measured load regulation is 2.3 mV/mA for maximum load current of 5 mA. The peak current efficiency of the proposed DF-LDO is 99.996 % with a maximum output voltage ripples value of 1.9 mV. The proposed digital LDO regulator active chip area is 0.012 mm<sup>2</sup>. |
| format | Article |
| id | doaj-art-371d46b4d2e8427e99960e56f4fcbf0b |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2021-01-01 |
| publisher | IEEE |
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| series | IEEE Access |
| spelling | doaj-art-371d46b4d2e8427e99960e56f4fcbf0b2025-01-30T00:00:57ZengIEEEIEEE Access2169-35362021-01-019281672817610.1109/ACCESS.2021.30572259347421Design of High Performance Hybrid Type Digital-Feedback Low Drop-Out Regulator Using SSCG TechniqueMuhammad Asif0https://orcid.org/0000-0002-4888-9721Imran Ali1https://orcid.org/0000-0002-4705-9988Danial Khan2https://orcid.org/0000-0003-4010-2637Muhammad Riaz Ur Rehman3https://orcid.org/0000-0002-2128-0115Younggun Pu4https://orcid.org/0000-0001-5190-4462Sang-Sun Yoo5https://orcid.org/0000-0001-5178-4392Kang-Yoon Lee6https://orcid.org/0000-0001-9777-6953Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaDepartment of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South KoreaThis paper proposes a high-performance Digital Feedback low-dropout voltage regulator (DF-LDO) for low power applications. In the DF-LDO regulator, digital feedback and applying spectrum spread clock generator (SSCG) technique are used to reduce output voltage ripples. In addition, it has triple operation modes i.e. coarse, fine, and retention for high efficiency and transient enhancement. The proposed hybrid DF-LDO uses arrays of PMOS transistors in coarse and fine mode whereas in retention mode, only one comparator and NMOS are active and digital controller goes into the sleep mode. This results in the reduction of the power consumption and improves the output voltage ripples. In the retention mode, minimum number of blocks operate that reduces the current consumption as compared to coarse and fine modes. To further reduce the current consumption, the comparator with hysteresis is used. The proposed circuit is designed using CMOS 55 nm process. The input voltage range is from 0.8 ~ 1.5 V and the measured output voltage range is 0.756 ~ 1.456 V. The measured line regulation is 6 mV / V, and the regulation starts when the input voltage is 0.8 V. The measured load regulation is 2.3 mV/mA for maximum load current of 5 mA. The peak current efficiency of the proposed DF-LDO is 99.996 % with a maximum output voltage ripples value of 1.9 mV. The proposed digital LDO regulator active chip area is 0.012 mm<sup>2</sup>.https://ieeexplore.ieee.org/document/9347421/Digital LDOfast settling timehybrid typelow quiescent currentSSCG technique |
| spellingShingle | Muhammad Asif Imran Ali Danial Khan Muhammad Riaz Ur Rehman Younggun Pu Sang-Sun Yoo Kang-Yoon Lee Design of High Performance Hybrid Type Digital-Feedback Low Drop-Out Regulator Using SSCG Technique IEEE Access Digital LDO fast settling time hybrid type low quiescent current SSCG technique |
| title | Design of High Performance Hybrid Type Digital-Feedback Low Drop-Out Regulator Using SSCG Technique |
| title_full | Design of High Performance Hybrid Type Digital-Feedback Low Drop-Out Regulator Using SSCG Technique |
| title_fullStr | Design of High Performance Hybrid Type Digital-Feedback Low Drop-Out Regulator Using SSCG Technique |
| title_full_unstemmed | Design of High Performance Hybrid Type Digital-Feedback Low Drop-Out Regulator Using SSCG Technique |
| title_short | Design of High Performance Hybrid Type Digital-Feedback Low Drop-Out Regulator Using SSCG Technique |
| title_sort | design of high performance hybrid type digital feedback low drop out regulator using sscg technique |
| topic | Digital LDO fast settling time hybrid type low quiescent current SSCG technique |
| url | https://ieeexplore.ieee.org/document/9347421/ |
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