Partially Isolated Dual Work Function Gate IGZO TFT With Obviously Reduced Leakage Current for 3D DRAMs
In this article, a partially isolated dual work function (PIDWF) gate In-Ga-Zn-O (IGZO) thin-film transistor (TFT) is proposed to reduce the off-state current (Ioff) obviously, which also provides a feasible integration method for stacking IGZO TFT on Si-based devices. It is found that compared with...
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| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10557586/ |
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| author | Yunjiao Bao Gangping Yan Lei Cao Chuqiao Niu Qingkun Li Guanqiao Sang Lianlian Li Yanzhao Wei Xuexiang Zhang Jie Luo Yanyu Yang Gaobo Xu Huaxiang Yin |
| author_facet | Yunjiao Bao Gangping Yan Lei Cao Chuqiao Niu Qingkun Li Guanqiao Sang Lianlian Li Yanzhao Wei Xuexiang Zhang Jie Luo Yanyu Yang Gaobo Xu Huaxiang Yin |
| author_sort | Yunjiao Bao |
| collection | DOAJ |
| description | In this article, a partially isolated dual work function (PIDWF) gate In-Ga-Zn-O (IGZO) thin-film transistor (TFT) is proposed to reduce the off-state current (Ioff) obviously, which also provides a feasible integration method for stacking IGZO TFT on Si-based devices. It is found that compared with the general back gate IGZO TFT structure, the Ioff of the proposed IGZO TFT reduces from <inline-formula> <tex-math notation="LaTeX">$2.57\times 10{^{-}14 }$ </tex-math></inline-formula> A/<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m to <inline-formula> <tex-math notation="LaTeX">$7.57\times 10{^{-}16 }$ </tex-math></inline-formula> A/<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m, achieving two orders of magnitude improvement. This breakthrough has the potential to increase the retention time of DRAM applications by nearly 100 times. Moreover, the pronounced novel structure has mitigated parasitic capacitance, thereby leading to a notable 47.7% reduction in write latency within dynamic-random-access-memory (DRAM) circuits. The relevant operation mechanism is carefully demonstrated and verified by the simulation of the electric field and potential barrier results by technical computer-aided design (TCAD). Furthermore, the impacts of the dual gate work function level, the length, and the type of isolation dielectric between dual work function gates are systematically investigated. The results show that the off-state leakage is further reduced by increasing the difference of the work function levels between in dual gates, the dielectric length (LD) and using the isolation layer with a lower dielectric constant. The PIDWF gate IGZO TFT exhibits scalability and is capable of achieving an 84.6% reduction in leakage current even with ultra-short channel lengths, which offers a promising application for future 3D DRAM applications with little extra cost. |
| format | Article |
| id | doaj-art-36b00619ee6f4e9dbf7272f0d1aff2a3 |
| institution | Kabale University |
| issn | 2168-6734 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj-art-36b00619ee6f4e9dbf7272f0d1aff2a32025-01-29T00:00:19ZengIEEEIEEE Journal of the Electron Devices Society2168-67342024-01-011263764410.1109/JEDS.2024.341446910557586Partially Isolated Dual Work Function Gate IGZO TFT With Obviously Reduced Leakage Current for 3D DRAMsYunjiao Bao0https://orcid.org/0009-0005-5381-9321Gangping Yan1https://orcid.org/0000-0002-5364-3224Lei Cao2https://orcid.org/0000-0002-0755-6488Chuqiao Niu3Qingkun Li4https://orcid.org/0009-0002-4764-7541Guanqiao Sang5https://orcid.org/0009-0002-0729-6863Lianlian Li6https://orcid.org/0009-0006-8143-1241Yanzhao Wei7https://orcid.org/0000-0003-0372-2423Xuexiang Zhang8https://orcid.org/0009-0002-7459-7826Jie Luo9https://orcid.org/0009-0003-6832-0238Yanyu Yang10Gaobo Xu11https://orcid.org/0000-0002-4278-251XHuaxiang Yin12https://orcid.org/0000-0001-8066-6002Key Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaKey Laboratory of Fabrication Technologies for Integrated Circuits, Chinese Academy of Sciences, Beijing, ChinaIn this article, a partially isolated dual work function (PIDWF) gate In-Ga-Zn-O (IGZO) thin-film transistor (TFT) is proposed to reduce the off-state current (Ioff) obviously, which also provides a feasible integration method for stacking IGZO TFT on Si-based devices. It is found that compared with the general back gate IGZO TFT structure, the Ioff of the proposed IGZO TFT reduces from <inline-formula> <tex-math notation="LaTeX">$2.57\times 10{^{-}14 }$ </tex-math></inline-formula> A/<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m to <inline-formula> <tex-math notation="LaTeX">$7.57\times 10{^{-}16 }$ </tex-math></inline-formula> A/<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula> m, achieving two orders of magnitude improvement. This breakthrough has the potential to increase the retention time of DRAM applications by nearly 100 times. Moreover, the pronounced novel structure has mitigated parasitic capacitance, thereby leading to a notable 47.7% reduction in write latency within dynamic-random-access-memory (DRAM) circuits. The relevant operation mechanism is carefully demonstrated and verified by the simulation of the electric field and potential barrier results by technical computer-aided design (TCAD). Furthermore, the impacts of the dual gate work function level, the length, and the type of isolation dielectric between dual work function gates are systematically investigated. The results show that the off-state leakage is further reduced by increasing the difference of the work function levels between in dual gates, the dielectric length (LD) and using the isolation layer with a lower dielectric constant. The PIDWF gate IGZO TFT exhibits scalability and is capable of achieving an 84.6% reduction in leakage current even with ultra-short channel lengths, which offers a promising application for future 3D DRAM applications with little extra cost.https://ieeexplore.ieee.org/document/10557586/Dual work function gateIn-Ga-Zn-O (IGZO) thin-fifilm transistor (TFT)isolation dielectricoff-state current (Ioff)partially isolated |
| spellingShingle | Yunjiao Bao Gangping Yan Lei Cao Chuqiao Niu Qingkun Li Guanqiao Sang Lianlian Li Yanzhao Wei Xuexiang Zhang Jie Luo Yanyu Yang Gaobo Xu Huaxiang Yin Partially Isolated Dual Work Function Gate IGZO TFT With Obviously Reduced Leakage Current for 3D DRAMs IEEE Journal of the Electron Devices Society Dual work function gate In-Ga-Zn-O (IGZO) thin-fifilm transistor (TFT) isolation dielectric off-state current (Ioff) partially isolated |
| title | Partially Isolated Dual Work Function Gate IGZO TFT With Obviously Reduced Leakage Current for 3D DRAMs |
| title_full | Partially Isolated Dual Work Function Gate IGZO TFT With Obviously Reduced Leakage Current for 3D DRAMs |
| title_fullStr | Partially Isolated Dual Work Function Gate IGZO TFT With Obviously Reduced Leakage Current for 3D DRAMs |
| title_full_unstemmed | Partially Isolated Dual Work Function Gate IGZO TFT With Obviously Reduced Leakage Current for 3D DRAMs |
| title_short | Partially Isolated Dual Work Function Gate IGZO TFT With Obviously Reduced Leakage Current for 3D DRAMs |
| title_sort | partially isolated dual work function gate igzo tft with obviously reduced leakage current for 3d drams |
| topic | Dual work function gate In-Ga-Zn-O (IGZO) thin-fifilm transistor (TFT) isolation dielectric off-state current (Ioff) partially isolated |
| url | https://ieeexplore.ieee.org/document/10557586/ |
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