Differential Evolution-Based End-Fire Realized Gain Optimization of Active and Parasitic Arrays
We propose a novel approach for boosting the realized gain of arrays with enhanced directivity, utilizing both active and parasitic dipoles. The optimization process first maximizes the end-fire gain in the active array by selecting the optimal current excitation vector. For the parasitic arrays, th...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10829613/ |
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| Summary: | We propose a novel approach for boosting the realized gain of arrays with enhanced directivity, utilizing both active and parasitic dipoles. The optimization process first maximizes the end-fire gain in the active array by selecting the optimal current excitation vector. For the parasitic arrays, the dipoles are reactively loaded based on the input impedances of the active dipoles, after which the optimization focuses on the inter-element distance to achieve a balance between the gain and the reflection efficiency. This multi-objective optimization, underpinned by the differential evolution (DE) algorithm, uses a simple wire dipole as the unit element. Full-wave simulations validate our theoretical results, showing that our two- and three-element parasitic arrays achieve realized gain comparable to state-of-the-art designs without relying on intricate unit elements or resource-intensive simulations, while our four- and five-element parasitic arrays yield the highest realized gain values reported in the literature. The simplicity of our approach allows optimizations to run significantly faster than full-wave simulations, whilst the sensitivity analysis showcases the robustness of the design under small deviations in loads and element positioning. Compact and power-efficient, the proposed parasitic arrays are well-suited for base stations, aligning with modern communication system requirements while minimizing hardware complexity. |
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| ISSN: | 2169-3536 |