Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s
The increasing demand for bandwidth in data centers is driving the advancement of wireline receivers to support higher data rates, even up to 224 Gb/s. A single-ended scheme, which utilizes two single-ended signals on a pair of differential channels, offers a promising solution for achieving this go...
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10757331/ |
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| author | Liping Zhong Quan Pan |
| author_facet | Liping Zhong Quan Pan |
| author_sort | Liping Zhong |
| collection | DOAJ |
| description | The increasing demand for bandwidth in data centers is driving the advancement of wireline receivers to support higher data rates, even up to 224 Gb/s. A single-ended scheme, which utilizes two single-ended signals on a pair of differential channels, offers a promising solution for achieving this goal. This approach effectively doubles the data throughput of the links and reduces the bandwidth requirements for both active and passive components. However, this scheme suffers from severe crosstalk, especially far-end crosstalk (FEXT). At higher data rates, single-ended crosstalk cancellation interfaces encounter several issues. First, FEXT noise becomes more pronounced at higher frequencies. Additionally, the increased bandwidth demands lead to higher power consumption. Finally, as frequency increases, the channel exhibits severe insertion loss, intensifying the equalization burden on receivers. This article introduces several techniques that enable single-ended crosstalk cancellation receivers to achieve data rates of up to 56 and 112 Gb/s per lane using four-level pulse amplitude modulation (PAM-4) in 28-nm CMOS technology. These 56 and 112 Gb/s receivers achieve a bit error rate of <<inline-formula> <tex-math notation="LaTeX">$10{^{-}10 }$ </tex-math></inline-formula> and <<inline-formula> <tex-math notation="LaTeX">$10{^{-}12 }$ </tex-math></inline-formula> with a single-ended channel loss of 24 and 25 dB, respectively. |
| format | Article |
| id | doaj-art-348e5ec33f64469ab5fb803f88e12342 |
| institution | Kabale University |
| issn | 2644-1349 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj-art-348e5ec33f64469ab5fb803f88e123422025-01-25T00:03:06ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492024-01-01431832710.1109/OJSSCS.2024.350231510757331Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/sLiping Zhong0https://orcid.org/0009-0008-3344-523XQuan Pan1https://orcid.org/0000-0001-8704-4505School of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaSchool of Microelectronics, Southern University of Science and Technology, Shenzhen, ChinaThe increasing demand for bandwidth in data centers is driving the advancement of wireline receivers to support higher data rates, even up to 224 Gb/s. A single-ended scheme, which utilizes two single-ended signals on a pair of differential channels, offers a promising solution for achieving this goal. This approach effectively doubles the data throughput of the links and reduces the bandwidth requirements for both active and passive components. However, this scheme suffers from severe crosstalk, especially far-end crosstalk (FEXT). At higher data rates, single-ended crosstalk cancellation interfaces encounter several issues. First, FEXT noise becomes more pronounced at higher frequencies. Additionally, the increased bandwidth demands lead to higher power consumption. Finally, as frequency increases, the channel exhibits severe insertion loss, intensifying the equalization burden on receivers. This article introduces several techniques that enable single-ended crosstalk cancellation receivers to achieve data rates of up to 56 and 112 Gb/s per lane using four-level pulse amplitude modulation (PAM-4) in 28-nm CMOS technology. These 56 and 112 Gb/s receivers achieve a bit error rate of <<inline-formula> <tex-math notation="LaTeX">$10{^{-}10 }$ </tex-math></inline-formula> and <<inline-formula> <tex-math notation="LaTeX">$10{^{-}12 }$ </tex-math></inline-formula> with a single-ended channel loss of 24 and 25 dB, respectively.https://ieeexplore.ieee.org/document/10757331/Backplane receivercrosstalk cancellation (XTC)far-end crosstalk (FEXT)pulse amplitude modulation (PAM-4)single-ended |
| spellingShingle | Liping Zhong Quan Pan Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s IEEE Open Journal of the Solid-State Circuits Society Backplane receiver crosstalk cancellation (XTC) far-end crosstalk (FEXT) pulse amplitude modulation (PAM-4) single-ended |
| title | Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s |
| title_full | Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s |
| title_fullStr | Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s |
| title_full_unstemmed | Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s |
| title_short | Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s |
| title_sort | design techniques for single ended wireline crosstalk cancellation receiver up to 112 gb s |
| topic | Backplane receiver crosstalk cancellation (XTC) far-end crosstalk (FEXT) pulse amplitude modulation (PAM-4) single-ended |
| url | https://ieeexplore.ieee.org/document/10757331/ |
| work_keys_str_mv | AT lipingzhong designtechniquesforsingleendedwirelinecrosstalkcancellationreceiverupto112gbs AT quanpan designtechniquesforsingleendedwirelinecrosstalkcancellationreceiverupto112gbs |