A 62-90 GHz High Linearity and Low Noise CMOS Mixer Using Transformer-Coupling Cascode Topology - Zhiqing Liu; Jiayu Dong; Zhilin Chen; Zhengdong Jiang; Pengxue Liu; Yunqiu Wu; Chenxi Zhao; Kai Kang (IEEE Access)
This paper presents a high linearity and low noise mixer for millimeter-wave applications in 65-nm CMOS process. A noise-reduction transformer with harmonic suppression is utilized and inserted between transconductance stage and switch stage to improve the linearity and noise figure (NF). Benefitted from the transformer-coupling cascode topology, the mixer can operate at a low supply voltage without sacrificing the linearity. In addition, this topology provides a great freedom for the choice of biases in transconductance stage and switch stage. Thus, linearity and noise performance can be further improved by optimizing the bias conditions of the two stages. According to experimental results, the proposed mixer exhibits a maximum conversion gain of 9.5 dB and a minimum single sideband NF of 9.2 dB with a local oscillator (LO) power of −3 dBm. The 3-dB bandwidth ranges from 62 to 90 GHz. The input 1-dB compression point ( $P_{1~dB}$ ) is −3.8 dBm at 77 GHz. Due to the compact and fully symmetrical layout, the LO-to-RF isolation is better than 48 dB.