Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic
State-of-the-art object recognition and pose estimation systems often utilize point feature algorithms, which in turn usually require the computing power of conventional PC hardware. In this paper, we describe two embedded systems for object detection and pose estimation using sophisticated point fe...
Saved in:
Main Authors: | Michael Schaeferling, Ulrich Hornung, Gundolf Kiefer |
---|---|
Format: | Article |
Language: | English |
Published: |
Wiley
2012-01-01
|
Series: | International Journal of Reconfigurable Computing |
Online Access: | http://dx.doi.org/10.1155/2012/368351 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
FPGA-QNN: Quantized Neural Network Hardware Acceleration on FPGAs
by: Mustafa Tasci, et al.
Published: (2025-01-01) -
Fuzzy Logic Based Hardware Accelerator with Partially Reconfigurable Defuzzification Stage for Image Edge Detection
by: Aous H. Kurdi, et al.
Published: (2017-01-01) -
Object Detection Post Processing Accelerator Based on Co-Design of Hardware and Software
by: Dengtian Yang, et al.
Published: (2025-01-01) -
AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC
by: Dominique Blouin, et al.
Published: (2011-01-01) -
Performance Evaluation of Heart Sound Cancellation in FPGA Hardware Implementation for Electronic Stethoscope
by: Chun-Tang Chao, et al.
Published: (2014-01-01)