Enhanced Performance of New Scaling-Free CORDIC for Memory-Based Fast Fourier Transform Architecture
Coordinate rotation digital computer (CORDIC) algorithm is an iterative method and it performs the vector rotation operation by micro-rotation with scaling operation in each iteration. This study introduces a high-performance power-efficient new scaling-free coordinate rotation digital computer (NSF...
Saved in:
| Main Authors: | , , , , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
|
| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10843669/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| Summary: | Coordinate rotation digital computer (CORDIC) algorithm is an iterative method and it performs the vector rotation operation by micro-rotation with scaling operation in each iteration. This study introduces a high-performance power-efficient new scaling-free coordinate rotation digital computer (NSF-CORDIC) algorithm to perform vector rotation operation in circular coordinates. The scaling operation required in the existing algorithm has been completely removed by the fourth-order approximation of Taylor series (TS). The number of iterations is reduced by an optimized shift value prediction technique for known and fixed angles, like the twiddle factor angle available in the fast Fourier transform (FFT) algorithm. The angle of convergence (AOC) of the algorithm is 57.1°, and it is extended to 180° using the pre-rotation operation and optimized shift value prediction technique. In addition to that, the new CORDIC cell architecture is designed to perform Taylor series-based iterations. Further, a memory-based FFT architecture is designed using a new CORDIC cell. In the FFT architecture, the CORDIC cell performs all the multiplication of twiddle factor. Therefore, the complex constant multiplier required to execute the twiddle factor multiplication is eliminated. The proposed architectures are implemented in the Zynq-7ZC706 FPGA board using the Vivado EDA tool. The scaling-free CORDIC cell architecture has 31% and 3% slice reduction, 72% and 45% slice delay product reduction, and 38% and 23% power reduction compared to the two different existing scaling-free CORDIC designs. The memory-based FFT architecture has 37.8% and 19.6% slice reduction, 38.4% and 27% slice delay product reduction, and 45% and 34% power reduction compared to the two different existing memory-based FFT architecture. |
|---|---|
| ISSN: | 2169-3536 |