A fault‐diagnosis and tolerant control technique for five‐level cascaded H‐bridge inverters
Abstract Reliability is a major concern for multilevel inverters (MLIs) in all industrial applications. The consequences of faults increase as the number of power semiconductor devices increases and may lead to serious damage to the overall system. To prevent such issues, an effective fault‐detectio...
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| Format: | Article |
| Language: | English |
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Wiley
2021-07-01
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| Series: | IET Circuits, Devices and Systems |
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| Online Access: | https://doi.org/10.1049/cds2.12033 |
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| author | Pavan Mehta Subhanarayan Sahoo Mayank Kumar |
| author_facet | Pavan Mehta Subhanarayan Sahoo Mayank Kumar |
| author_sort | Pavan Mehta |
| collection | DOAJ |
| description | Abstract Reliability is a major concern for multilevel inverters (MLIs) in all industrial applications. The consequences of faults increase as the number of power semiconductor devices increases and may lead to serious damage to the overall system. To prevent such issues, an effective fault‐detection technique is required. A detailed analysis is presented of five‐level cascaded H‐bridge MLIs under healthy and faulty conditions. A fault‐detection technique based on total harmonic distortion and a normalized output voltage factor is presented. Also discussed is a fault‐isolation technique based on reduction of amplitude modulation, which results in a fault‐tolerant inverter. The level‐shifted pulse‐width modulation (LSPWM) technique is used for switching operation. LSPWM is most suitable for MLIs that require less computational effort. The presented fault‐diagnosis technique can be implemented on MLI‐based drives, grid‐connected operations etc. without any major changes. The simulation and hardware results are presented to validate the proposed fault‐detection and fault‐tolerant control technique at different power factors. |
| format | Article |
| id | doaj-art-2e19f78ade5642828aabfa6b134c5383 |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2021-07-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-2e19f78ade5642828aabfa6b134c53832025-02-03T01:29:39ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982021-07-0115436637610.1049/cds2.12033A fault‐diagnosis and tolerant control technique for five‐level cascaded H‐bridge invertersPavan Mehta0Subhanarayan Sahoo1Mayank Kumar2Electrical Engineering Department Gujarat Technological University Ahmedabad IndiaElectrical Engineering Department Adani Institute of Infrastructure Engineering Ahmedabad IndiaElectrical Engineering Department Delhi Technological University Delhi IndiaAbstract Reliability is a major concern for multilevel inverters (MLIs) in all industrial applications. The consequences of faults increase as the number of power semiconductor devices increases and may lead to serious damage to the overall system. To prevent such issues, an effective fault‐detection technique is required. A detailed analysis is presented of five‐level cascaded H‐bridge MLIs under healthy and faulty conditions. A fault‐detection technique based on total harmonic distortion and a normalized output voltage factor is presented. Also discussed is a fault‐isolation technique based on reduction of amplitude modulation, which results in a fault‐tolerant inverter. The level‐shifted pulse‐width modulation (LSPWM) technique is used for switching operation. LSPWM is most suitable for MLIs that require less computational effort. The presented fault‐diagnosis technique can be implemented on MLI‐based drives, grid‐connected operations etc. without any major changes. The simulation and hardware results are presented to validate the proposed fault‐detection and fault‐tolerant control technique at different power factors.https://doi.org/10.1049/cds2.12033bridge circuitsfault diagnosisfault toleranceharmonic distortionpower factorpower grids |
| spellingShingle | Pavan Mehta Subhanarayan Sahoo Mayank Kumar A fault‐diagnosis and tolerant control technique for five‐level cascaded H‐bridge inverters IET Circuits, Devices and Systems bridge circuits fault diagnosis fault tolerance harmonic distortion power factor power grids |
| title | A fault‐diagnosis and tolerant control technique for five‐level cascaded H‐bridge inverters |
| title_full | A fault‐diagnosis and tolerant control technique for five‐level cascaded H‐bridge inverters |
| title_fullStr | A fault‐diagnosis and tolerant control technique for five‐level cascaded H‐bridge inverters |
| title_full_unstemmed | A fault‐diagnosis and tolerant control technique for five‐level cascaded H‐bridge inverters |
| title_short | A fault‐diagnosis and tolerant control technique for five‐level cascaded H‐bridge inverters |
| title_sort | fault diagnosis and tolerant control technique for five level cascaded h bridge inverters |
| topic | bridge circuits fault diagnosis fault tolerance harmonic distortion power factor power grids |
| url | https://doi.org/10.1049/cds2.12033 |
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