Digital Phase-Locked Loops: Exploring Different Boundaries
This article examines the research area of digital phase-locked loops (DPLLs), a critical component in modern electronic systems, from wireless communication devices to RADAR systems and digital processors. As the demands for higher integration levels in electronic systems increase, DPLLs have becom...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10684740/ |
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| author | Yuncheng Zhang Dingxin Xu Kenichi Okada |
| author_facet | Yuncheng Zhang Dingxin Xu Kenichi Okada |
| author_sort | Yuncheng Zhang |
| collection | DOAJ |
| description | This article examines the research area of digital phase-locked loops (DPLLs), a critical component in modern electronic systems, from wireless communication devices to RADAR systems and digital processors. As the demands for higher integration levels in electronic systems increase, DPLLs have become a key point for research and development. Implemented in scaled digital CMOS process, DPLLs offer potential advantages over traditional analog designs and have explored the boundaries of phaselocked loop (PLL) design. This article delves into several key directions of DPLL research: improvements in PLL performance through digital methods, the automation of PLL design using commercial electronic design automation (EDA) tools, and innovative approaches for using low-frequency references in wireless applications. Specifically, it covers the DPLL architectures using time-to-digital and digital-to-time converters, as well as bang–bang phase detectors, fully synthesizable DPLLs, and the integration of oversampling techniques that enable the use of a 32-kHz reference to avoid using bulky higher-frequency reference sources. This review outlines current achievements of DPLLs research in these directions. |
| format | Article |
| id | doaj-art-2ace7564802e4a4abec47222e2603580 |
| institution | Kabale University |
| issn | 2644-1349 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj-art-2ace7564802e4a4abec47222e26035802025-01-25T00:03:17ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492024-01-01417619210.1109/OJSSCS.2024.346455110684740Digital Phase-Locked Loops: Exploring Different BoundariesYuncheng Zhang0https://orcid.org/0000-0001-6467-3667Dingxin Xu1https://orcid.org/0000-0003-4691-2147Kenichi Okada2https://orcid.org/0000-0002-1082-7672Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, Tokyo, JapanDepartment of Electrical and Electronic Engineering, Tokyo Institute of Technology, Tokyo, JapanDepartment of Electrical and Electronic Engineering, Tokyo Institute of Technology, Tokyo, JapanThis article examines the research area of digital phase-locked loops (DPLLs), a critical component in modern electronic systems, from wireless communication devices to RADAR systems and digital processors. As the demands for higher integration levels in electronic systems increase, DPLLs have become a key point for research and development. Implemented in scaled digital CMOS process, DPLLs offer potential advantages over traditional analog designs and have explored the boundaries of phaselocked loop (PLL) design. This article delves into several key directions of DPLL research: improvements in PLL performance through digital methods, the automation of PLL design using commercial electronic design automation (EDA) tools, and innovative approaches for using low-frequency references in wireless applications. Specifically, it covers the DPLL architectures using time-to-digital and digital-to-time converters, as well as bang–bang phase detectors, fully synthesizable DPLLs, and the integration of oversampling techniques that enable the use of a 32-kHz reference to avoid using bulky higher-frequency reference sources. This review outlines current achievements of DPLLs research in these directions.https://ieeexplore.ieee.org/document/10684740/ADPLLbang–bang phase detectorCMOSdigitaldigital-to-time converterfully synthesizable PLL |
| spellingShingle | Yuncheng Zhang Dingxin Xu Kenichi Okada Digital Phase-Locked Loops: Exploring Different Boundaries IEEE Open Journal of the Solid-State Circuits Society ADPLL bang–bang phase detector CMOS digital digital-to-time converter fully synthesizable PLL |
| title | Digital Phase-Locked Loops: Exploring Different Boundaries |
| title_full | Digital Phase-Locked Loops: Exploring Different Boundaries |
| title_fullStr | Digital Phase-Locked Loops: Exploring Different Boundaries |
| title_full_unstemmed | Digital Phase-Locked Loops: Exploring Different Boundaries |
| title_short | Digital Phase-Locked Loops: Exploring Different Boundaries |
| title_sort | digital phase locked loops exploring different boundaries |
| topic | ADPLL bang–bang phase detector CMOS digital digital-to-time converter fully synthesizable PLL |
| url | https://ieeexplore.ieee.org/document/10684740/ |
| work_keys_str_mv | AT yunchengzhang digitalphaselockedloopsexploringdifferentboundaries AT dingxinxu digitalphaselockedloopsexploringdifferentboundaries AT kenichiokada digitalphaselockedloopsexploringdifferentboundaries |