An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

We describe the architecture of a time-to-digital converter (TDC), specially intended to measure the delay resolution of a programmable delay line (PDL). The configuration, which consists of a ring oscillator, a frequency divider (FD), and a period measurement circuit (PMC), is implemented in a fiel...

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Bibliographic Details
Main Authors: Chao Chen, Shengwei Meng, Zhenghuan Xia, Guangyou Fang, Hejun Yin
Format: Article
Language:English
Published: Wiley 2014-01-01
Series:Journal of Electrical and Computer Engineering
Online Access:http://dx.doi.org/10.1155/2014/230803
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