An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement
We describe the architecture of a time-to-digital converter (TDC), specially intended to measure the delay resolution of a programmable delay line (PDL). The configuration, which consists of a ring oscillator, a frequency divider (FD), and a period measurement circuit (PMC), is implemented in a fiel...
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| Format: | Article |
| Language: | English |
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Wiley
2014-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2014/230803 |
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| author | Chao Chen Shengwei Meng Zhenghuan Xia Guangyou Fang Hejun Yin |
| author_facet | Chao Chen Shengwei Meng Zhenghuan Xia Guangyou Fang Hejun Yin |
| author_sort | Chao Chen |
| collection | DOAJ |
| description | We describe the architecture of a time-to-digital converter (TDC), specially intended to measure the delay resolution of a programmable delay line (PDL). The configuration, which consists of a ring oscillator, a frequency divider (FD), and a period measurement circuit (PMC), is implemented in a field programmable gate array (FPGA) device. The ring oscillator realized in loop containing a PDL and a look-up table (LUT) generates periodic oscillatory pulses. The FD amplifies the oscillatory period from nanosecond range to microsecond range. The time-to-digital conversion is based on counting the number of clock cycles between two consecutive pulses of the FD by the PMC. Experiments have been conducted to verify the performance of the TDC. The achieved relative errors for four PDLs are within 0.50%–1.21% and the TDC has an equivalent resolution of about 0.4 ps. |
| format | Article |
| id | doaj-art-278bdc24ec7143a0af7bf794fb602a98 |
| institution | Kabale University |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2014-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-278bdc24ec7143a0af7bf794fb602a982025-02-03T06:45:26ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552014-01-01201410.1155/2014/230803230803An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution MeasurementChao Chen0Shengwei Meng1Zhenghuan Xia2Guangyou Fang3Hejun Yin4Key Laboratory of Electromagnetic Radiation and Sensing Technology, Chinese Academy of Sciences, No. 19, North 4th Ring Road West, Haidian District, Beijing 100190, ChinaKey Laboratory of Electromagnetic Radiation and Sensing Technology, Chinese Academy of Sciences, No. 19, North 4th Ring Road West, Haidian District, Beijing 100190, ChinaKey Laboratory of Electromagnetic Radiation and Sensing Technology, Chinese Academy of Sciences, No. 19, North 4th Ring Road West, Haidian District, Beijing 100190, ChinaKey Laboratory of Electromagnetic Radiation and Sensing Technology, Chinese Academy of Sciences, No. 19, North 4th Ring Road West, Haidian District, Beijing 100190, ChinaChinese Academy of Sciences, 52 Sanlihe Road, Beijing 100864, ChinaWe describe the architecture of a time-to-digital converter (TDC), specially intended to measure the delay resolution of a programmable delay line (PDL). The configuration, which consists of a ring oscillator, a frequency divider (FD), and a period measurement circuit (PMC), is implemented in a field programmable gate array (FPGA) device. The ring oscillator realized in loop containing a PDL and a look-up table (LUT) generates periodic oscillatory pulses. The FD amplifies the oscillatory period from nanosecond range to microsecond range. The time-to-digital conversion is based on counting the number of clock cycles between two consecutive pulses of the FD by the PMC. Experiments have been conducted to verify the performance of the TDC. The achieved relative errors for four PDLs are within 0.50%–1.21% and the TDC has an equivalent resolution of about 0.4 ps.http://dx.doi.org/10.1155/2014/230803 |
| spellingShingle | Chao Chen Shengwei Meng Zhenghuan Xia Guangyou Fang Hejun Yin An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement Journal of Electrical and Computer Engineering |
| title | An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement |
| title_full | An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement |
| title_fullStr | An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement |
| title_full_unstemmed | An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement |
| title_short | An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement |
| title_sort | fpga integrated time to digital converter based on a ring oscillator for programmable delay line resolution measurement |
| url | http://dx.doi.org/10.1155/2014/230803 |
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