3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans
We propose new 3D 2-layer and 3-layer NoC architectures that utilize homogeneous regular mesh networks on a separate layer and one or two heterogeneous floorplanning layers. These architectures combine the benefits of compact heterogeneous floorplans and of regular mesh networks. To demonstrate thes...
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| Format: | Article |
| Language: | English |
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Wiley
2010-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2010/603059 |
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| _version_ | 1832560586044473344 |
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| author | Vitor de Paulo Cristinel Ababei |
| author_facet | Vitor de Paulo Cristinel Ababei |
| author_sort | Vitor de Paulo |
| collection | DOAJ |
| description | We propose new 3D 2-layer and 3-layer NoC architectures that utilize homogeneous regular mesh
networks on a separate layer and one or two heterogeneous
floorplanning layers. These architectures combine the benefits
of compact heterogeneous floorplans and of regular mesh networks.
To demonstrate these benefits, a design methodology that
integrates floorplanning, routers assignment, and cycle-accurate
NoC simulation is proposed. The implementation of the NoC on
a separate layer offers an additional area that may be utilized to
improve the network performance by increasing the number of
virtual channels, buffers size, or mesh size. Experimental results
show that increasing the number of virtual channels rather than
the buffers size has a higher impact on network performance.
Increasing the mesh size can significantly improve the network
performance under the assumption that the clock frequency is
given by the length of the physical links. In addition, the 3-layer
architecture can offer significantly better network performance
compared to the 2-layer architecture. |
| format | Article |
| id | doaj-art-26eea8fc16544608a014311b4d221d05 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2010-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-26eea8fc16544608a014311b4d221d052025-02-03T01:27:14ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092010-01-01201010.1155/2010/6030596030593D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous FloorplansVitor de Paulo0Cristinel Ababei1Electrical and Computer Engineering Department, North Dakota State University, Fargo, ND 58108-6050, USAElectrical and Computer Engineering Department, North Dakota State University, Fargo, ND 58108-6050, USAWe propose new 3D 2-layer and 3-layer NoC architectures that utilize homogeneous regular mesh networks on a separate layer and one or two heterogeneous floorplanning layers. These architectures combine the benefits of compact heterogeneous floorplans and of regular mesh networks. To demonstrate these benefits, a design methodology that integrates floorplanning, routers assignment, and cycle-accurate NoC simulation is proposed. The implementation of the NoC on a separate layer offers an additional area that may be utilized to improve the network performance by increasing the number of virtual channels, buffers size, or mesh size. Experimental results show that increasing the number of virtual channels rather than the buffers size has a higher impact on network performance. Increasing the mesh size can significantly improve the network performance under the assumption that the clock frequency is given by the length of the physical links. In addition, the 3-layer architecture can offer significantly better network performance compared to the 2-layer architecture.http://dx.doi.org/10.1155/2010/603059 |
| spellingShingle | Vitor de Paulo Cristinel Ababei 3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans International Journal of Reconfigurable Computing |
| title | 3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans |
| title_full | 3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans |
| title_fullStr | 3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans |
| title_full_unstemmed | 3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans |
| title_short | 3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans |
| title_sort | 3d network on chip architectures using homogeneous meshes and heterogeneous floorplans |
| url | http://dx.doi.org/10.1155/2010/603059 |
| work_keys_str_mv | AT vitordepaulo 3dnetworkonchiparchitecturesusinghomogeneousmeshesandheterogeneousfloorplans AT cristinelababei 3dnetworkonchiparchitecturesusinghomogeneousmeshesandheterogeneousfloorplans |