A 0.002‐mm2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC)
Abstract Digital‐to‐analogue converters (DACs) are essential blocks for interfacing the digital environment with the real world. A novel architecture, using a digital‐to‐time converter (DTC) and a time‐to‐voltage converter (TVC), is employed to form a low‐power time‐based DAC (T‐DAC) that fits low‐p...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2021-11-01
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| Series: | IET Circuits, Devices and Systems |
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| Online Access: | https://doi.org/10.1049/cds2.12068 |
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| _version_ | 1832546790577012736 |
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| author | Ali H. Hassan Hassan Mostafa Mohamed Refky Khaled N. Salama Ahmed M. Soliman |
| author_facet | Ali H. Hassan Hassan Mostafa Mohamed Refky Khaled N. Salama Ahmed M. Soliman |
| author_sort | Ali H. Hassan |
| collection | DOAJ |
| description | Abstract Digital‐to‐analogue converters (DACs) are essential blocks for interfacing the digital environment with the real world. A novel architecture, using a digital‐to‐time converter (DTC) and a time‐to‐voltage converter (TVC), is employed to form a low‐power time‐based DAC (T‐DAC) that fits low‐power low‐speed applications. This novel conversion mixes the digital input code into a digital pulse width modulated (D‐PWM) signal through the DTC circuit, then converts this D‐PWM signal into an analogue voltage through the TVC circuit. This new T‐DAC is not only an energy‐efficient design but also an area‐efficient implementation. Power optimization is achieved by controlling the supply voltage of the TVC circuit with a discontinuous waveform using a low bias current. Moreover, the implementation area is optimized by proposing a new DAC architecture with a coarse‐fine DTC circuit. Post‐layout simulations of the proposed T‐DAC is conducted using industrial hardware‐calibrated 0.13 μm. Complementary metal oxide semiconductor technology with a 1 V supply voltage, 1 MS/s conversion rate, and 0.9 μW power dissipation. |
| format | Article |
| id | doaj-art-23e2c0fcad9a4072940ce6d0595e888a |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2021-11-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-23e2c0fcad9a4072940ce6d0595e888a2025-02-03T06:47:11ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982021-11-0115873874410.1049/cds2.12068A 0.002‐mm2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC)Ali H. Hassan0Hassan Mostafa1Mohamed Refky2Khaled N. Salama3Ahmed M. Soliman4Electronics and Communications Engineering Department Faculty of Engineering Cairo University Giza EgyptElectronics and Communications Engineering Department Faculty of Engineering Cairo University Giza EgyptElectronics and Communications Engineering Department Faculty of Engineering Cairo University Giza EgyptDivision of Computer, Electrical and Mathematical Sciences & Engineering King Abdullah University of Science and Technology Thuwal Saudi ArabiaElectronics and Communications Engineering Department Faculty of Engineering Cairo University Giza EgyptAbstract Digital‐to‐analogue converters (DACs) are essential blocks for interfacing the digital environment with the real world. A novel architecture, using a digital‐to‐time converter (DTC) and a time‐to‐voltage converter (TVC), is employed to form a low‐power time‐based DAC (T‐DAC) that fits low‐power low‐speed applications. This novel conversion mixes the digital input code into a digital pulse width modulated (D‐PWM) signal through the DTC circuit, then converts this D‐PWM signal into an analogue voltage through the TVC circuit. This new T‐DAC is not only an energy‐efficient design but also an area‐efficient implementation. Power optimization is achieved by controlling the supply voltage of the TVC circuit with a discontinuous waveform using a low bias current. Moreover, the implementation area is optimized by proposing a new DAC architecture with a coarse‐fine DTC circuit. Post‐layout simulations of the proposed T‐DAC is conducted using industrial hardware‐calibrated 0.13 μm. Complementary metal oxide semiconductor technology with a 1 V supply voltage, 1 MS/s conversion rate, and 0.9 μW power dissipation.https://doi.org/10.1049/cds2.12068low‐power electronicsCMOS integrated circuitsdigital‐analogue conversiontime‐digital conversionpulse width modulationcircuit optimisation |
| spellingShingle | Ali H. Hassan Hassan Mostafa Mohamed Refky Khaled N. Salama Ahmed M. Soliman A 0.002‐mm2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC) IET Circuits, Devices and Systems low‐power electronics CMOS integrated circuits digital‐analogue conversion time‐digital conversion pulse width modulation circuit optimisation |
| title | A 0.002‐mm2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC) |
| title_full | A 0.002‐mm2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC) |
| title_fullStr | A 0.002‐mm2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC) |
| title_full_unstemmed | A 0.002‐mm2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC) |
| title_short | A 0.002‐mm2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC) |
| title_sort | 0 002 mm2 8 bit 1 ms s low power time based dac t dac |
| topic | low‐power electronics CMOS integrated circuits digital‐analogue conversion time‐digital conversion pulse width modulation circuit optimisation |
| url | https://doi.org/10.1049/cds2.12068 |
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